hour_out.vhd

来自「FPGA设计的时钟！很特别」· VHDL 代码 · 共 35 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hour_out is
	port ( set : in std_logic;       
		   alarm  : in std_logic;      
		 hour24_0  ,    hour24_1:     in std_logic_vector(3 downto 0);
          hour_set_0,hour_set_1: in std_logic_vector(3 downto 0);
           hour_a_0  , hour_a_1:  in std_logic_vector(3 downto 0);
           hour0_out , hour1_out: out std_logic_vector(3 downto 0));    
end hour_out;

architecture arch of hour_out is
	signal hour0_tmp,hour1_tmp : std_logic_vector(3 downto 0);
 begin
      process ( set,alarm) 			
       begin
         if ( set='1' ) then        
			hour0_tmp<=hour_set_0;
			hour1_tmp<=hour_set_1;
		 elsif ( alarm ='1' ) then	
			hour0_tmp<=hour_a_0;
			hour1_tmp<=hour_a_1;			
             else			       
                   hour0_tmp<= hour24_0;
			       hour1_tmp<=hour24_1;
             end if;
     end process;
	hour0_out<=hour0_tmp;
	hour1_out<=hour1_tmp;

end  architecture arch;