📄 hour_out.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 5/ 48( 10%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
B: 8/ 96( 8%) 0/ 48( 0%) 7/ 48( 14%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
** EQUATIONS **
alarm : INPUT;
hour_a_00 : INPUT;
hour_a_01 : INPUT;
hour_a_02 : INPUT;
hour_a_03 : INPUT;
hour_a_10 : INPUT;
hour_a_11 : INPUT;
hour_a_12 : INPUT;
hour_a_13 : INPUT;
hour_set_00 : INPUT;
hour_set_01 : INPUT;
hour_set_02 : INPUT;
hour_set_03 : INPUT;
hour_set_10 : INPUT;
hour_set_11 : INPUT;
hour_set_12 : INPUT;
hour_set_13 : INPUT;
hour24_00 : INPUT;
hour24_01 : INPUT;
hour24_02 : INPUT;
hour24_03 : INPUT;
hour24_10 : INPUT;
hour24_11 : INPUT;
hour24_12 : INPUT;
hour24_13 : INPUT;
set : INPUT;
-- Node name is 'hour0_out0'
-- Equation name is 'hour0_out0', type is output
hour0_out0 = _LC1_B13;
-- Node name is 'hour0_out1'
-- Equation name is 'hour0_out1', type is output
hour0_out1 = _LC5_B13;
-- Node name is 'hour0_out2'
-- Equation name is 'hour0_out2', type is output
hour0_out2 = _LC3_B13;
-- Node name is 'hour0_out3'
-- Equation name is 'hour0_out3', type is output
hour0_out3 = _LC8_B13;
-- Node name is 'hour1_out0'
-- Equation name is 'hour1_out0', type is output
hour1_out0 = _LC1_A12;
-- Node name is 'hour1_out1'
-- Equation name is 'hour1_out1', type is output
hour1_out1 = _LC7_A12;
-- Node name is 'hour1_out2'
-- Equation name is 'hour1_out2', type is output
hour1_out2 = _LC2_A12;
-- Node name is 'hour1_out3'
-- Equation name is 'hour1_out3', type is output
hour1_out3 = _LC8_A12;
-- Node name is ':178'
-- Equation name is '_LC7_B13', type is buried
_LC7_B13 = LCELL( _EQ001);
_EQ001 = alarm & hour_a_03
# !alarm & hour24_03;
-- Node name is ':184'
-- Equation name is '_LC8_B13', type is buried
_LC8_B13 = LCELL( _EQ002);
_EQ002 = _LC7_B13 & !set
# hour_set_03 & set;
-- Node name is ':190'
-- Equation name is '_LC6_B13', type is buried
_LC6_B13 = LCELL( _EQ003);
_EQ003 = alarm & hour_a_02
# !alarm & hour24_02;
-- Node name is ':193'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ004);
_EQ004 = _LC6_B13 & !set
# hour_set_02 & set;
-- Node name is ':199'
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ005);
_EQ005 = alarm & hour_a_01
# !alarm & hour24_01;
-- Node name is ':202'
-- Equation name is '_LC5_B13', type is buried
_LC5_B13 = LCELL( _EQ006);
_EQ006 = _LC4_B13 & !set
# hour_set_01 & set;
-- Node name is ':208'
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ007);
_EQ007 = alarm & hour_a_00
# !alarm & hour24_00;
-- Node name is ':211'
-- Equation name is '_LC1_B13', type is buried
_LC1_B13 = LCELL( _EQ008);
_EQ008 = _LC2_B13 & !set
# hour_set_00 & set;
-- Node name is ':217'
-- Equation name is '_LC6_A12', type is buried
_LC6_A12 = LCELL( _EQ009);
_EQ009 = alarm & hour_a_13
# !alarm & hour24_13;
-- Node name is ':220'
-- Equation name is '_LC8_A12', type is buried
_LC8_A12 = LCELL( _EQ010);
_EQ010 = _LC6_A12 & !set
# hour_set_13 & set;
-- Node name is ':226'
-- Equation name is '_LC5_A12', type is buried
_LC5_A12 = LCELL( _EQ011);
_EQ011 = alarm & hour_a_12
# !alarm & hour24_12;
-- Node name is ':229'
-- Equation name is '_LC2_A12', type is buried
_LC2_A12 = LCELL( _EQ012);
_EQ012 = _LC5_A12 & !set
# hour_set_12 & set;
-- Node name is ':235'
-- Equation name is '_LC4_A12', type is buried
_LC4_A12 = LCELL( _EQ013);
_EQ013 = alarm & hour_a_11
# !alarm & hour24_11;
-- Node name is ':238'
-- Equation name is '_LC7_A12', type is buried
_LC7_A12 = LCELL( _EQ014);
_EQ014 = _LC4_A12 & !set
# hour_set_11 & set;
-- Node name is ':244'
-- Equation name is '_LC3_A12', type is buried
_LC3_A12 = LCELL( _EQ015);
_EQ015 = alarm & hour_a_10
# !alarm & hour24_10;
-- Node name is ':247'
-- Equation name is '_LC1_A12', type is buried
_LC1_A12 = LCELL( _EQ016);
_EQ016 = _LC3_A12 & !set
# hour_set_10 & set;
Project Information d:\my_own_works\digit_clock\hour_out.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 19,422K
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