📄 hour_out.rpt
字号:
Project Information d:\my_own_works\digit_clock\hour_out.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 10/15/2005 11:02:45
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
HOUR_OUT
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
hour_out EPF10K10LC84-3 26 8 0 0 0 % 16 2 %
User Pins: 26 8 0
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
***** Logic for device 'hour_out' compiled without errors.
Device: EPF10K10LC84-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
h h h
o h o h o ^
h u o u h o h u C
R R R o R r R u r o u R o R r O
E E E u E _ E r _ u r E u E _ N
S S S r S s S V 1 s r 0 G S r S s F
E E E 2 E e E C _ a e 2 _ N E 2 E e _ ^
R R R 4 R t R C o l t 4 o D R 4 R t # D n
V V V _ V _ V I u a _ _ u I V _ V _ T O C
E E E 1 E 1 E N t r 1 1 t N E 0 E 0 C N E
D D D 3 D 1 D T 3 m 0 0 3 T D 3 D 0 K E O
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
^DATA0 | 12 74 | #TDO
^DCLK | 13 73 | hour_a_13
^nCE | 14 72 | hour_a_12
#TDI | 15 71 | hour_set_13
hour1_out0 | 16 70 | hour_set_12
hour1_out2 | 17 69 | hour24_12
hour24_11 | 18 68 | GNDINT
hour1_out1 | 19 67 | hour0_out0
VCCINT | 20 66 | hour0_out2
hour_a_02 | 21 65 | hour0_out1
hour24_01 | 22 EPF10K10LC84-3 64 | hour_a_03
hour24_02 | 23 63 | VCCINT
hour24_00 | 24 62 | RESERVED
hour_a_01 | 25 61 | RESERVED
GNDINT | 26 60 | RESERVED
RESERVED | 27 59 | RESERVED
RESERVED | 28 58 | RESERVED
RESERVED | 29 57 | #TMS
RESERVED | 30 56 | #TRST
^MSEL0 | 31 55 | ^nSTATUS
^MSEL1 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
V ^ R R R R R V G s h h V G h R h h h R R
C n E E E E E C N e o o C N o E o o o E E
C C S S S S S C D t u u C D u S u u u S S
I O E E E E E I I r r I I r E r r r E E
N N R R R R R N N _ _ N N _ R _ _ _ R R
T F V V V V V T T a a T T s V s a s V V
I E E E E E _ _ e E e _ e E E
G D D D D D 1 1 t D t 0 t D D
1 0 _ _ 0 _
0 0 0
2 3 1
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A12 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
B13 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 28/53 ( 52%)
Total logic cells used: 16/576 ( 2%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.00/4 ( 75%)
Total fan-in: 48/2304 ( 2%)
Total input pins required: 26
Total input I/O cell registers required: 0
Total output pins required: 8
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 16
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 8/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 16/0
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
2 - - - -- INPUT 0 0 0 8 alarm
50 - - - 17 INPUT 0 0 0 1 hour_a_00
25 - - B -- INPUT 0 0 0 1 hour_a_01
21 - - B -- INPUT 0 0 0 1 hour_a_02
64 - - B -- INPUT 0 0 0 1 hour_a_03
44 - - - -- INPUT 0 0 0 1 hour_a_10
43 - - - -- INPUT 0 0 0 1 hour_a_11
72 - - A -- INPUT 0 0 0 1 hour_a_12
73 - - A -- INPUT 0 0 0 1 hour_a_13
78 - - - 24 INPUT 0 0 0 1 hour_set_00
51 - - - 18 INPUT 0 0 0 1 hour_set_01
47 - - - 14 INPUT 0 0 0 1 hour_set_02
49 - - - 16 INPUT 0 0 0 1 hour_set_03
1 - - - -- INPUT 0 0 0 1 hour_set_10
6 - - - 04 INPUT 0 0 0 1 hour_set_11
70 - - A -- INPUT 0 0 0 1 hour_set_12
71 - - A -- INPUT 0 0 0 1 hour_set_13
24 - - B -- INPUT 0 0 0 1 hour24_00
22 - - B -- INPUT 0 0 0 1 hour24_01
23 - - B -- INPUT 0 0 0 1 hour24_02
80 - - - 23 INPUT 0 0 0 1 hour24_03
84 - - - -- INPUT 0 0 0 1 hour24_10
18 - - A -- INPUT 0 0 0 1 hour24_11
69 - - A -- INPUT 0 0 0 1 hour24_12
8 - - - 03 INPUT 0 0 0 1 hour24_13
42 - - - -- INPUT 0 0 0 8 set
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - B -- OUTPUT 0 1 0 0 hour0_out0
65 - - B -- OUTPUT 0 1 0 0 hour0_out1
66 - - B -- OUTPUT 0 1 0 0 hour0_out2
83 - - - 13 OUTPUT 0 1 0 0 hour0_out3
16 - - A -- OUTPUT 0 1 0 0 hour1_out0
19 - - A -- OUTPUT 0 1 0 0 hour1_out1
17 - - A -- OUTPUT 0 1 0 0 hour1_out2
3 - - - 12 OUTPUT 0 1 0 0 hour1_out3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - B 13 OR2 3 0 0 1 :178
- 8 - B 13 OR2 2 1 1 0 :184
- 6 - B 13 OR2 3 0 0 1 :190
- 3 - B 13 OR2 2 1 1 0 :193
- 4 - B 13 OR2 3 0 0 1 :199
- 5 - B 13 OR2 2 1 1 0 :202
- 2 - B 13 OR2 3 0 0 1 :208
- 1 - B 13 OR2 2 1 1 0 :211
- 6 - A 12 OR2 3 0 0 1 :217
- 8 - A 12 OR2 2 1 1 0 :220
- 5 - A 12 OR2 3 0 0 1 :226
- 2 - A 12 OR2 2 1 1 0 :229
- 4 - A 12 OR2 3 0 0 1 :235
- 7 - A 12 OR2 2 1 1 0 :238
- 3 - A 12 OR2 3 0 0 1 :244
- 1 - A 12 OR2 2 1 1 0 :247
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\my_own_works\digit_clock\hour_out.rpt
hour_out
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -