jtd.twr
来自「交通灯控制,在A和B方向各用数码管显示剩余的时间.」· TWR 代码 · 共 56 行
TWR
56 行
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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml jtd jtd.ncd -o jtd.twr
jtd.pcf
Design file: jtd.ncd
Physical constraint file: jtd.pcf
Device,speed: xc2s50,-5 (PRODUCTION 1.27 2003-12-13)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock clk to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
A_G | 16.550(R)|clk_BUFGP | 0.000|
A_L | 15.541(R)|clk_BUFGP | 0.000|
A_R | 14.951(R)|clk_BUFGP | 0.000|
A_Y | 14.949(R)|clk_BUFGP | 0.000|
B_G | 16.430(R)|clk_BUFGP | 0.000|
B_L | 15.424(R)|clk_BUFGP | 0.000|
B_R | 13.855(R)|clk_BUFGP | 0.000|
B_Y | 15.191(R)|clk_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk | 8.397| | | |
---------------+---------+---------+---------+---------+
Analysis completed Tue Apr 10 20:58:58 2007
--------------------------------------------------------------------------------
Peak Memory Usage: 46 MB
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