jtd.syr

来自「交通灯控制,在A和B方向各用数码管显示剩余的时间.」· SYR 代码 · 共 339 行

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
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--> Reading design: jtd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : jtd.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : jtd
Output Format                      : NGC
Target Device                      : xc2s50-5-tq144

---- Source Options
Top Module Name                    : jtd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : jtd.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/JIAOTONG/JTD.vhdl in Library work.
Architecture behavioral of Entity jtd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <jtd> (Architecture <behavioral>).
Entity <jtd> analyzed. Unit <jtd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <jtd>.
    Related source file is E:/VHDL/JIAOTONG/JTD.vhdl.
    Found finite state machine <FSM_0> for signal <CR_STATE>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 9                                              |
    | Inputs             | 0                                              |
    | Outputs            | 17                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | rr                                             |
    | Power Up State     | rr                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 6-bit latch for signal <CT_TIME>.
WARNING:Xst:737 - Found 3-bit latch for signal <AXS>.
    Found 6-bit comparator equal for signal <$n0001> created at line 45.
    Found 6-bit up counter for signal <COUNT>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <jtd> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CR_STATE> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Counters                         : 1
 6-bit up counter                  : 1
# Registers                        : 9
 1-bit register                    : 9
# Latches                          : 2
 3-bit latch                       : 1
 6-bit latch                       : 1
# Comparators                      : 1
 6-bit comparator equal            : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <CT_TIME_0> is constant in block <jtd>.

Optimizing unit <jtd> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jtd, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : jtd.ngr
Top Level Output File Name         : jtd
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# Counters                         : 1
#      6-bit up counter            : 1
# Comparators                      : 1
#      6-bit comparator equal      : 1

Cell Usage :
# BELS                             : 49
#      GND                         : 1
#      LUT1                        : 1
#      LUT1_L                      : 1
#      LUT2                        : 4
#      LUT3                        : 7
#      LUT3_L                      : 6
#      LUT4                        : 10
#      LUT4_L                      : 3
#      MUXCY                       : 9
#      VCC                         : 1
#      XORCY                       : 6
# FlipFlops/Latches                : 23
#      FDCE                        : 8
#      FDCPE                       : 6
#      FDPE                        : 1
#      LD_1                        : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      19  out of    768     2%  
 Number of Slice Flip Flops:            23  out of   1536     1%  
 Number of 4 input LUTs:                32  out of   1536     2%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
SF668(SF6681:O)                    | NONE(*)(AXS_2)         | 3     |
CR_STATE_FFd9:Q                    | NONE                   | 5     |
clk                                | BUFGP                  | 15    |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 9.909ns (Maximum Frequency: 100.918MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.488ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               9.909ns (Levels of Logic = 12)
  Source:            COUNT_0 (FF)
  Destination:       COUNT_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: COUNT_0 to COUNT_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   1.292   1.340  COUNT_0 (COUNT_0)
     LUT4_L:I0->LO         1   0.653   0.000  Mcompar__n0001_inst_lut4_01 (Mcompar__n0001_inst_lut4_0)
     MUXCY:S->O            1   0.784   0.000  Mcompar__n0001_inst_cy_0 (Mcompar__n0001_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  Mcompar__n0001_inst_cy_1 (Mcompar__n0001_inst_cy_1)
     MUXCY:CI->O          16   0.050   2.800  Mcompar__n0001_inst_cy_2 (_n0001)
     LUT1_L:I0->LO         1   0.653   0.000  _n0001_rt (_n0001_rt)
     MUXCY:S->O            1   0.784   0.000  COUNT_inst_cy_3 (COUNT_inst_cy_3)
     MUXCY:CI->O           1   0.050   0.000  COUNT_inst_cy_4 (COUNT_inst_cy_4)
     MUXCY:CI->O           1   0.050   0.000  COUNT_inst_cy_5 (COUNT_inst_cy_5)
     MUXCY:CI->O           1   0.050   0.000  COUNT_inst_cy_6 (COUNT_inst_cy_6)
     MUXCY:CI->O           1   0.050   0.000  COUNT_inst_cy_7 (COUNT_inst_cy_7)
     MUXCY:CI->O           0   0.050   0.000  COUNT_inst_cy_8 (COUNT_inst_cy_8)
     XORCY:CI->O           1   0.500   0.000  COUNT_inst_sum_5 (COUNT_inst_sum_5)
     FDCPE:D                   0.753          COUNT_5
    ----------------------------------------
    Total                      9.909ns (5.769ns logic, 4.140ns route)
                                       (58.2% logic, 41.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              14.488ns (Levels of Logic = 4)
  Source:            CR_STATE_FFd3 (FF)
  Destination:       A_L (PAD)
  Source Clock:      clk rising

  Data Path: CR_STATE_FFd3 to A_L
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             6   1.292   1.850  CR_STATE_FFd3 (CR_STATE_FFd3)
     LUT4:I2->O            2   0.653   1.340  SF6551 (SF655)
     LUT4:I3->O            2   0.653   1.340  SF6571 (SF657)
     LUT2:I1->O            1   0.653   1.150  CR_STATE_Out131 (A_L_OBUF)
     OBUF:I->O                 5.557          A_L_OBUF (A_L)
    ----------------------------------------
    Total                     14.488ns (8.808ns logic, 5.680ns route)
                                       (60.8% logic, 39.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'SF6681:O'
Offset:              8.128ns (Levels of Logic = 1)
  Source:            AXS_2 (LATCH)
  Destination:       AXS<2> (PAD)
  Source Clock:      SF6681:O rising

  Data Path: AXS_2 to AXS<2>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD_1:G->Q             1   1.421   1.150  AXS_2 (AXS_2)
     OBUF:I->O                 5.557          AXS_2_OBUF (AXS<2>)
    ----------------------------------------
    Total                      8.128ns (6.978ns logic, 1.150ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 2.75 / 4.03 s | Elapsed : 3.00 / 4.00 s
 
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Total memory usage is 56428 kilobytes