jt.syr

交通灯控制,在A和B方向各用数码管显示剩余的时间.

# Counters                         : 10
 17-bit up counter                 : 1
 2-bit up counter                  : 1
 26-bit up counter                 : 1
 4-bit up counter                  : 4
 6-bit up counter                  : 3
# Registers                        : 19
 1-bit register                    : 13
 4-bit register                    : 4
 6-bit register                    : 2
# Latches                          : 2
 3-bit latch                       : 1
 6-bit latch                       : 1
# Comparators                      : 13
 17-bit comparator greatequal      : 1
 17-bit comparator lessequal       : 3
 26-bit comparator greatequal      : 1
 26-bit comparator lessequal       : 3
 6-bit comparator equal            : 1
 6-bit comparator greatequal       : 2
 6-bit comparator less             : 2
# Multiplexers                     : 4
 1-bit 4-to-1 multiplexer          : 2
 4-bit 4-to-1 multiplexer          : 2
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1988 - Unit <fengliwei>: instances <Mcompar__n0015>, <Mcompar__n0013> of unit <LPM_COMPARE_8> and unit <LPM_COMPARE_7> are dual, second instance is removed
WARNING:Xst:1988 - Unit <fengliwei>: instances <Mcompar__n0014>, <Mcompar__n0012> of unit <LPM_COMPARE_8> and unit <LPM_COMPARE_7> are dual, second instance is removed
WARNING:Xst:1989 - Unit <f1s>: instances <Mcompar__n0001>, <Mcompar__n0005> of unit <LPM_COMPARE_4> are equivalent, second instance is removed
WARNING:Xst:1989 - Unit <fpq10ms>: instances <Mcompar__n0001>, <Mcompar__n0005> of unit <LPM_COMPARE_1> are equivalent, second instance is removed
WARNING:Xst:1293 - FF/Latch  <CT_TIME_0> has a constant value of 0 in block <jtd>.
WARNING:Xst:2041 - Unit f1s: 1 internal tristate is replaced by logic (pull-up yes): CP.
WARNING:Xst:2041 - Unit fpq10ms: 1 internal tristate is replaced by logic (pull-up yes): CP.

Optimizing unit <JT> ...

Optimizing unit <jtd> ...

Optimizing unit <djs> ...

Optimizing unit <fpq10ms> ...

Optimizing unit <f1s> ...

Optimizing unit <fengliwei> ...
Loading device for application Rf_Device from file 'v50.nph' in environment C:/Xilinx7.1.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block JT, actual ratio is 23.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : JT.ngr
Top Level Output File Name         : JT
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 21

Macro Statistics :
# ROMs                             : 1
#      16x7-bit ROM                : 1
# Registers                        : 19
#      1-bit register              : 4
#      2-bit register              : 9
#      4-bit register              : 4
#      6-bit register              : 2
# Counters                         : 1
#      6-bit up counter            : 1
# Multiplexers                     : 4
#      1-bit 4-to-1 multiplexer    : 2
#      4-bit 4-to-1 multiplexer    : 2
# Tristates                        : 2
#      1-bit tristate buffer       : 2
# Adders/Subtractors               : 2
#      6-bit subtractor            : 2
# Comparators                      : 13
#      17-bit comparator greatequal: 1
#      17-bit comparator lessequal : 3
#      26-bit comparator greatequal: 1
#      26-bit comparator lessequal : 3
#      6-bit comparator equal      : 1
#      6-bit comparator greatequal : 2
#      6-bit comparator less       : 2

Cell Usage :
# BELS                             : 487
#      GND                         : 1
#      INV                         : 37
#      LUT1                        : 51
#      LUT1_L                      : 17
#      LUT2                        : 22
#      LUT2_L                      : 38
#      LUT3                        : 25
#      LUT3_L                      : 12
#      LUT4                        : 40
#      LUT4_D                      : 10
#      LUT4_L                      : 23
#      MUXCY                       : 137
#      MUXF5                       : 4
#      VCC                         : 1
#      XORCY                       : 69
# FlipFlops/Latches                : 128
#      FD                          : 4
#      FDCE                        : 8
#      FDCPE                       : 6
#      FDE                         : 16
#      FDPE                        : 1
#      FDR                         : 67
#      FDRE                        : 8
#      FDS                         : 10
#      LD_1                        : 8
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 20
#      IBUF                        : 1
#      OBUF                        : 19
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                     195  out of    768    25%  
 Number of Slice Flip Flops:           128  out of   1536     8%  
 Number of 4 input LUTs:               238  out of   1536    15%  
 Number of bonded IOBs:                 21  out of     96    21%  
 Number of GCLKs:                        3  out of      4    75%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_321(XLXI_36_CPLogicTrst1:O)   | BUFG(*)(XLXI_4_COUNT_5)| 27    |
XLXN_241(XLXI_51_CPLogicTrst1:O)   | BUFG(*)(XLXI_9_bge_3)  | 46    |
XLXI_4__n0021(XLXI_4__n00211:O)    | NONE(*)(XLXI_4_AXS_2)  | 3     |
XLXI_4_CR_STATE_FFd9:Q             | NONE                   | 5     |
CLK                                | BUFGP                  | 47    |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.455ns (Maximum Frequency: 95.648MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 14.230ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_36_CPLogicTrst1:O'
  Clock period: 9.959ns (frequency: 100.412MHz)
  Total number of paths / destination ports: 446 / 43
-------------------------------------------------------------------------
Delay:               9.959ns (Levels of Logic = 13)
  Source:            XLXI_4_COUNT_0 (FF)
  Destination:       XLXI_4_COUNT_5 (FF)
  Source Clock:      XLXI_36_CPLogicTrst1:O rising
  Destination Clock: XLXI_36_CPLogicTrst1:O rising

  Data Path: XLXI_4_COUNT_0 to XLXI_4_COUNT_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   1.292   1.340  XLXI_4_COUNT_0 (XLXI_4_COUNT_0)
     INV:I->O              1   0.653   0.000  XLXI_4_norlut_INV_0 (XLXI_4_N2)
     MUXCY:S->O            1   0.784   0.000  XLXI_4_norcy (XLXI_4_nor_cyo)
     MUXCY:CI->O           1   0.050   0.000  XLXI_4_Eq_stagecy (XLXI_4_Eq_stage_cyo)
     MUXCY:CI->O           1   0.050   0.000  XLXI_4_Eq_stagecy_rn_0 (XLXI_4_Eq_stage_cyo1)
     MUXCY:CI->O          16   0.050   2.800  XLXI_4_Eq_stagecy_rn_1 (XLXI_4__n0001)
     LUT1_L:I0->LO         1   0.653   0.000  XLXI_4__n0001_rt (XLXI_4__n0001_rt)
     MUXCY:S->O            1   0.784   0.000  XLXI_4_COUNT_inst_cy_0 (XLXI_4_COUNT_inst_cy_0)
     MUXCY:CI->O           1   0.050   0.000  XLXI_4_COUNT_inst_cy_1 (XLXI_4_COUNT_inst_cy_1)
     MUXCY:CI->O           1   0.050   0.000  XLXI_4_COUNT_inst_cy_2 (XLXI_4_COUNT_inst_cy_2)
     MUXCY:CI->O           1   0.050   0.000  XLXI_4_COUNT_inst_cy_3 (XLXI_4_COUNT_inst_cy_3)
     MUXCY:CI->O           1   0.050   0.000  XLXI_4_COUNT_inst_cy_4 (XLXI_4_COUNT_inst_cy_4)
     MUXCY:CI->O           0   0.050   0.000  XLXI_4_COUNT_inst_cy_5 (XLXI_4_COUNT_inst_cy_5)
     XORCY:CI->O           1   0.500   0.000  XLXI_4_COUNT_inst_sum_5 (XLXI_4_COUNT_inst_sum_5)
     FDCPE:D                   0.753          XLXI_4_COUNT_5
    ----------------------------------------
    Total                      9.959ns (5.819ns logic, 4.140ns route)
                                       (58.4% logic, 41.6% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'XLXI_51_CPLogicTrst1:O'
  Clock period: 10.455ns (frequency: 95.648MHz)
  Total number of paths / destination ports: 697 / 100
-------------------------------------------------------------------------
Delay:               10.455ns (Levels of Logic = 8)
  Source:            XLXI_9_comb1_0 (FF)
  Destination:       XLXI_9_comb1a_2 (FF)
  Source Clock:      XLXI_51_CPLogicTrst1:O rising
  Destination Clock: XLXI_51_CPLogicTrst1:O rising

  Data Path: XLXI_9_comb1_0 to XLXI_9_comb1a_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              2   1.292   1.340  XLXI_9_comb1_0 (XLXI_9_comb1_0)
     LUT2_L:I0->LO         1   0.653   0.000  XLXI_9_XNor_stagelut6 (XLXI_9_N14)
     MUXCY:S->O            1   0.784   0.000  XLXI_9_XNor_stagecy_rn_5 (XLXI_9_XNor_stage_cyo5)
     MUXCY:CI->O           1   0.050   0.000  XLXI_9_XNor_stagecy_rn_6 (XLXI_9_XNor_stage_cyo6)
     MUXCY:CI->O           1   0.050   0.000  XLXI_9_XNor_stagecy_rn_7 (XLXI_9_XNor_stage_cyo7)
     MUXCY:CI->O           1   0.050   0.000  XLXI_9_XNor_stagecy_rn_8 (XLXI_9_XNor_stage_cyo8)
     MUXCY:CI->O           1   0.050   0.000  XLXI_9_XNor_stagecy_rn_9 (XLXI_9_XNor_stage_cyo9)
     MUXCY:CI->O          19   0.050   3.100  XLXI_9_XNor_stagecy_rn_10 (XLXI_9__n0014)
     LUT2:I0->O            4   0.653   1.600  XLXI_9__n00082 (XLXI_9__n0008)
     FDR:R                     0.783          XLXI_9_comb1a_0
    ----------------------------------------
    Total                     10.455ns (4.415ns logic, 6.040ns route)
                                       (42.2% logic, 57.8% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 10.314ns (frequency: 96.956MHz)
  Total number of paths / destination ports: 1591 / 92
-------------------------------------------------------------------------
Delay:               10.314ns (Levels of Logic = 3)
  Source:            XLXI_36_a_25 (FF)
  Destination:       XLXI_36_a_0 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: XLXI_36_a_25 to XLXI_36_a_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              5   1.292   1.740  XLXI_36_a_25 (XLXI_36_a_25)
     LUT4:I0->O            1   0.653   1.150  XLXI_36__n000255 (CHOICE832)
     LUT4_D:I0->O          2   0.653   1.340  XLXI_36__n000299 (CHOICE847)
     LUT4:I3->O            8   0.653   2.050  XLXI_36__n0002112 (XLXI_36__n0002)
     FDR:R                     0.783          XLXI_36_a_0
    ----------------------------------------
    Total                     10.314ns (4.034ns logic, 6.280ns route)
                                       (39.1% logic, 60.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_36_CPLogicTrst1:O'
  Total number of paths / destination ports: 16 / 8
-------------------------------------------------------------------------
Offset:              10.702ns (Levels of Logic = 2)
  Source:            XLXI_4_CR_STATE_FFd2 (FF)
  Destination:       BL (PAD)
  Source Clock:      XLXI_36_CPLogicTrst1:O rising

  Data Path: XLXI_4_CR_STATE_FFd2 to BL
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             8   1.292   2.050  XLXI_4_CR_STATE_FFd2 (XLXI_4_CR_STATE_FFd2)
     LUT4:I2->O            1   0.653   1.150  XLXI_4_CR_STATE_Out101 (BR_OBUF)
     OBUF:I->O                 5.557          BR_OBUF (BR)
    ----------------------------------------
    Total                     10.702ns (7.502ns logic, 3.200ns route)
                                       (70.1% logic, 29.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_51_CPLogicTrst1:O'
  Total number of paths / destination ports: 204 / 11
-------------------------------------------------------------------------
Offset:              14.230ns (Levels of Logic = 4)
  Source:            XLXI_5_b_1 (FF)
  Destination:       SEG<6> (PAD)
  Source Clock:      XLXI_51_CPLogicTrst1:O rising

  Data Path: XLXI_5_b_1 to SEG<6>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q             14   1.292   2.600  XLXI_5_b_1 (XLXI_5_b_1)
     LUT3:I0->O            1   0.653   0.000  XLXI_52_Mmux_Q_XLXN_90<0>_XLXN_90<0>111_F (N529)
     MUXF5:I0->O           7   0.375   1.950  XLXI_52_Mmux_Q_XLXN_90<0>_XLXN_90<0>111 (XLXN_90<1>)
     LUT4:I0->O            1   0.653   1.150  XLXI_38_Mrom_Q_inst_lut4_01 (SEG_0_OBUF)
     OBUF:I->O                 5.557          SEG_0_OBUF (SEG<0>)
    ----------------------------------------
    Total                     14.230ns (8.530ns logic, 5.700ns route)
                                       (59.9% logic, 40.1% route)

=========================================================================
CPU : 16.95 / 17.77 s | Elapsed : 17.00 / 17.00 s
 
--> 

Total memory usage is 88980 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   11 (   0 filtered)
Number of infos    :    2 (   0 filtered)