jt.syr

交通灯控制,在A和B方向各用数码管显示剩余的时间.

Release 7.1i - xst H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: JT.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "JT.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "JT"
Output Format                      : NGC
Target Device                      : xc2s50-5-tq144

---- Source Options
Top Module Name                    : JT
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : JT.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/DJS.vhdl" in Library work.
Architecture behavioral of Entity djs is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/JTD.vhdl" in Library work.
Architecture behavioral of Entity jtd is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/SE41.vhdl" in Library work.
Architecture behavioral of Entity se is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/FENLIWEI.vhdl" in Library work.
Architecture behavioral of Entity fengliwei is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/f1s.vhdl" in Library work.
Architecture behavioral of Entity f1s is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/YMQ1.vhdl" in Library work.
Architecture behavioral of Entity ymq1 is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/FPQ2MS.vhdl" in Library work.
Architecture behavioral of Entity fpq10ms is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/xzqwo.vhdl" in Library work.
Architecture behavioral of Entity xzq5 is up to date.
Compiling vhdl file "F:/dragon/VHDL/myboard/JIAOTONG/JT.vhf" in Library work.
Architecture behavioral of Entity jt is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <JT> (Architecture <behavioral>).
Entity <JT> analyzed. Unit <JT> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
WARNING:Xst:819 - "F:/dragon/VHDL/myboard/JIAOTONG/DJS.vhdl" line 23: The following signals are missing in the process sensitivity list:
   count1, count2.
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <jtd> (Architecture <behavioral>).
Entity <jtd> analyzed. Unit <jtd> generated.

Analyzing Entity <se> (Architecture <behavioral>).
Entity <se> analyzed. Unit <se> generated.

Analyzing Entity <fengliwei> (Architecture <behavioral>).
Entity <fengliwei> analyzed. Unit <fengliwei> generated.

Analyzing Entity <f1s> (Architecture <behavioral>).
Entity <f1s> analyzed. Unit <f1s> generated.

Analyzing Entity <ymq1> (Architecture <behavioral>).
Entity <ymq1> analyzed. Unit <ymq1> generated.

Analyzing Entity <fpq10ms> (Architecture <behavioral>).
Entity <fpq10ms> analyzed. Unit <fpq10ms> generated.

Analyzing Entity <xzq5> (Architecture <behavioral>).
WARNING:Xst:819 - "F:/dragon/VHDL/myboard/JIAOTONG/xzqwo.vhdl" line 24: The following signals are missing in the process sensitivity list:
   Q1, Q2, Q3, Q4.
Entity <xzq5> analyzed. Unit <xzq5> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <xzq5>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/xzqwo.vhdl".
    Found 4-bit 4-to-1 multiplexer for signal <Q>.
    Found 4-bit 4-to-1 multiplexer for signal <sel>.
    Summary:
	inferred   8 Multiplexer(s).
Unit <xzq5> synthesized.


Synthesizing Unit <fpq10ms>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/FPQ2MS.vhdl".
    Found 1-bit tristate buffer for signal <CP>.
    Found 17-bit comparator lessequal for signal <$n0001>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0003>.
    Found 17-bit comparator lessequal for signal <$n0005>.
    Found 17-bit comparator greatequal for signal <$n0007>.
    Found 17-bit comparator lessequal for signal <$n0008>.
    Found 17-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   1 Multiplexer(s).
	inferred   1 Tristate(s).
Unit <fpq10ms> synthesized.


Synthesizing Unit <ymq1>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/YMQ1.vhdl".
    Found 16x7-bit ROM for signal <Q>.
    Summary:
	inferred   1 ROM(s).
Unit <ymq1> synthesized.


Synthesizing Unit <f1s>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/f1s.vhdl".
    Found 1-bit tristate buffer for signal <CP>.
    Found 26-bit comparator lessequal for signal <$n0001>.
    Found 1-bit 4-to-1 multiplexer for signal <$n0003>.
    Found 26-bit comparator lessequal for signal <$n0005>.
    Found 26-bit comparator greatequal for signal <$n0007>.
    Found 26-bit comparator lessequal for signal <$n0008>.
    Found 26-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred   1 Multiplexer(s).
	inferred   1 Tristate(s).
Unit <f1s> synthesized.


Synthesizing Unit <fengliwei>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/FENLIWEI.vhdl".
    Found 4-bit register for signal <ashi>.
    Found 4-bit register for signal <age>.
    Found 4-bit register for signal <bshi>.
    Found 4-bit register for signal <bge>.
    Found 6-bit comparator less for signal <$n0012> created at line 27.
    Found 6-bit comparator less for signal <$n0013> created at line 51.
    Found 6-bit comparator greatequal for signal <$n0014> created at line 27.
    Found 6-bit comparator greatequal for signal <$n0015> created at line 51.
    Found 6-bit up counter for signal <comb1>.
    Found 4-bit up counter for signal <comb1a>.
    Found 4-bit up counter for signal <comb1b>.
    Found 6-bit up counter for signal <comb2>.
    Found 4-bit up counter for signal <comb2a>.
    Found 4-bit up counter for signal <comb2b>.
    Summary:
	inferred   6 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <fengliwei> synthesized.


Synthesizing Unit <se>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/SE41.vhdl".
    Found 2-bit up counter for signal <b>.
    Summary:
	inferred   1 Counter(s).
Unit <se> synthesized.


Synthesizing Unit <jtd>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/JTD.vhdl".
    Found finite state machine <FSM_0> for signal <CR_STATE>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 9                                              |
    | Inputs             | 0                                              |
    | Outputs            | 17                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | rr                                             |
    | Power Up State     | rr                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 6-bit latch for signal <CT_TIME>.
WARNING:Xst:737 - Found 3-bit latch for signal <AXS>.
    Found 6-bit comparator equal for signal <$n0001> created at line 45.
    Found 6-bit up counter for signal <COUNT>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <jtd> synthesized.


Synthesizing Unit <djs>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/DJS.vhdl".
    Found 6-bit subtractor for signal <$n0010>.
    Found 6-bit subtractor for signal <$n0011>.
    Found 6-bit register for signal <count1>.
    Found 6-bit register for signal <count2>.
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <djs> synthesized.


Synthesizing Unit <JT>.
    Related source file is "F:/dragon/VHDL/myboard/JIAOTONG/JT.vhf".
Unit <JT> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <CR_STATE[1:9]> with one-hot encoding.
--------------------
 State | Encoding
--------------------
 rr    | 000000001
 gr    | 000000010
 yr1   | 000000100
 yr2   | 000010000
 lr    | 000001000
 rg    | 000100000
 ry1   | 001000000
 ry2   | 100000000
 rl    | 010000000
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 2
 6-bit subtractor                  : 2