__projnav.log

交通灯控制,在A和B方向各用数码管显示剩余的时间.

    Related source file is E:/VHDL/JIAOTONG/f05ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <f05ms> synthesized.


Synthesizing Unit <fengliwei>.
    Related source file is E:/VHDL/JIAOTONG/FENLIWEI.vhdl.
    Found 4-bit register for signal <ashi>.
    Found 4-bit register for signal <age>.
    Found 4-bit register for signal <bshi>.
    Found 4-bit register for signal <bge>.
    Found 6-bit comparator greatequal for signal <$n0012> created at line 27.
    Found 6-bit comparator less for signal <$n0013> created at line 27.
    Found 6-bit comparator greatequal for signal <$n0014> created at line 51.
    Found 6-bit comparator less for signal <$n0015> created at line 51.
    Found 6-bit up counter for signal <comb1>.
    Found 4-bit up counter for signal <comb1a>.
    Found 4-bit up counter for signal <comb1b>.
    Found 6-bit up counter for signal <comb2>.
    Found 4-bit up counter for signal <comb2a>.
    Found 4-bit up counter for signal <comb2b>.
    Summary:
	inferred   6 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <fengliwei> synthesized.


Synthesizing Unit <se>.
    Related source file is E:/VHDL/JIAOTONG/SE41.vhdl.
    Found 2-bit up counter for signal <b>.
    Summary:
	inferred   1 Counter(s).
Unit <se> synthesized.


Synthesizing Unit <jtd>.
    Related source file is E:/VHDL/JIAOTONG/JTD.vhdl.
    Found finite state machine <FSM_0> for signal <CR_STATE>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 9                                              |
    | Inputs             | 0                                              |
    | Outputs            | 13                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | rr                                             |
    | Power Up State     | rr                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 6-bit latch for signal <CT_TIME>.
WARNING:Xst:737 - Found 3-bit latch for signal <AXS>.
    Found 6-bit comparator equal for signal <$n0001> created at line 45.
    Found 6-bit up counter for signal <COUNT>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <jtd> synthesized.


Synthesizing Unit <djs>.
    Related source file is E:/VHDL/JIAOTONG/DJS.vhdl.
    Found 6-bit subtractor for signal <$n0010>.
    Found 6-bit subtractor for signal <$n0011>.
    Found 6-bit register for signal <count1>.
    Found 6-bit register for signal <count2>.
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <djs> synthesized.


Synthesizing Unit <jt>.
    Related source file is E:/VHDL/JIAOTONG/JT.vhf.
Unit <jt> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CR_STATE> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 2
 6-bit subtractor                  : 2
# Counters                         : 10
 6-bit up counter                  : 3
 4-bit up counter                  : 4
 15-bit up counter                 : 1
 26-bit up counter                 : 1
 2-bit up counter                  : 1
# Registers                        : 19
 6-bit register                    : 2
 4-bit register                    : 4
 1-bit register                    : 13
# Latches                          : 2
 3-bit latch                       : 1
 6-bit latch                       : 1
# Comparators                      : 11
 6-bit comparator equal            : 1
 6-bit comparator less             : 2
 6-bit comparator greatequal       : 2
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
 26-bit comparator lessequal       : 2
 26-bit comparator greatequal      : 1
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <CT_TIME_0> is constant in block <jtd>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <jt> ...

Optimizing unit <djs> ...

Optimizing unit <jtd> ...

Optimizing unit <fengliwei> ...

Optimizing unit <f05ms> ...

Optimizing unit <f1s> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jt, actual ratio is 23.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                     187  out of    768    24%  
 Number of Slice Flip Flops:           126  out of   1536     8%  
 Number of 4 input LUTs:               296  out of   1536    19%  
 Number of bonded IOBs:                 20  out of     96    20%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_24(XLXI_35_I3_0:O)            | NONE(*)(XLXI_9_ashi_2) | 46    |
CLK                                | BUFGP                  | 45    |
XLXN_32(XLXI_36_I3_0:O)            | NONE(*)(XLXI_4_CR_STATE_FFd4)| 27    |
XLXI_4__n0021(XLXI_4__n00211:O)    | NONE(*)(XLXI_4_AXS_1)  | 3     |
XLXI_4_CR_STATE_FFd9:Q             | NONE                   | 5     |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 10.884ns (Maximum Frequency: 91.878MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 13.830ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\jiaotong/_ngo -uc YJ2.ucf -p
xc2s50-tq144-5 jt.ngc jt.ngd 

Reading NGO file "E:/VHDL/JIAOTONG/jt.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "YJ2.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40164 kilobytes

Writing NGD file "jt.ngd" ...

Writing NGDBUILD log file "jt.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\jiaotong/_ngo -uc YJ2.ucf -p
xc2s50-tq144-5 jt.ngc jt.ngd 

Reading NGO file "E:/VHDL/JIAOTONG/jt.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "YJ2.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 42212 kilobytes

Writing NGD file "jt.ngd" ...

Writing NGDBUILD log file "jt.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Total Number Slice Registers:     126 out of  1,536    8%
    Number used as Flip Flops:                    118
    Number used as Latches:                         8
  Number of 4 input LUTs:           208 out of  1,536   13%
Logic Distribution:
    Number of occupied Slices:                         171 out of    768   22%
    Number of Slices containing only related logic:    171 out of    171  100%
    Number of Slices containing unrelated logic:         0 out of    171    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          292 out of  1,536   19%
      Number used as logic:                       208
      Number used as a route-thru:                 84
   Number of bonded IOBs:            20 out of     92   21%
   Number of Tbufs:                   2 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  2,997
Additional JTAG gate count for IOBs:  1,008
Peak Memory Usage:  61 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "jt_map.mrp" for details.
Completed process "Map".

Mapping Module jt . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-5 -cm area -pr b -k 4 -c 100 -tx off -o jt_map.ncd jt.ngd jt.pcf
Mapping Module jt: DONE



Started process "Place & Route".





Constraints file: jt.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "jt_map.ncd".
   "jt" is an NCD, version 2.38, device xc2s50, package tq144, speed -5
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical