__projnav.log

交通灯控制,在A和B方向各用数码管显示剩余的时间.

    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <f1s> synthesized.


Synthesizing Unit <f05ms>.
    Related source file is E:/VHDL/JIAOTONG/f05ms.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <f05ms> synthesized.


Synthesizing Unit <fengliwei>.
    Related source file is E:/VHDL/JIAOTONG/FENLIWEI.vhdl.
    Found 4-bit register for signal <ashi>.
    Found 4-bit register for signal <age>.
    Found 4-bit register for signal <bshi>.
    Found 4-bit register for signal <bge>.
    Found 6-bit comparator greatequal for signal <$n0012> created at line 27.
    Found 6-bit comparator less for signal <$n0013> created at line 27.
    Found 6-bit comparator greatequal for signal <$n0014> created at line 51.
    Found 6-bit comparator less for signal <$n0015> created at line 51.
    Found 6-bit up counter for signal <comb1>.
    Found 4-bit up counter for signal <comb1a>.
    Found 4-bit up counter for signal <comb1b>.
    Found 6-bit up counter for signal <comb2>.
    Found 4-bit up counter for signal <comb2a>.
    Found 4-bit up counter for signal <comb2b>.
    Summary:
	inferred   6 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <fengliwei> synthesized.


Synthesizing Unit <se>.
    Related source file is E:/VHDL/JIAOTONG/SE41.vhdl.
    Found 2-bit up counter for signal <b>.
    Summary:
	inferred   1 Counter(s).
Unit <se> synthesized.


Synthesizing Unit <jtd>.
    Related source file is E:/VHDL/JIAOTONG/JTD.vhdl.
    Found finite state machine <FSM_0> for signal <CR_STATE>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 9                                              |
    | Inputs             | 0                                              |
    | Outputs            | 13                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | rst (negative)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | rr                                             |
    | Power Up State     | rr                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 6-bit latch for signal <CT_TIME>.
WARNING:Xst:737 - Found 3-bit latch for signal <AXS>.
    Found 6-bit comparator equal for signal <$n0001> created at line 45.
    Found 6-bit up counter for signal <COUNT>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <jtd> synthesized.


Synthesizing Unit <djs>.
    Related source file is E:/VHDL/JIAOTONG/DJS.vhdl.
    Found 6-bit subtractor for signal <$n0010>.
    Found 6-bit subtractor for signal <$n0011>.
    Found 6-bit register for signal <count1>.
    Found 6-bit register for signal <count2>.
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <djs> synthesized.


Synthesizing Unit <jt>.
    Related source file is E:/VHDL/JIAOTONG/JT.vhf.
Unit <jt> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CR_STATE> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# ROMs                             : 1
 16x7-bit ROM                      : 1
# Adders/Subtractors               : 2
 6-bit subtractor                  : 2
# Counters                         : 10
 6-bit up counter                  : 3
 4-bit up counter                  : 4
 15-bit up counter                 : 1
 26-bit up counter                 : 1
 2-bit up counter                  : 1
# Registers                        : 19
 6-bit register                    : 2
 4-bit register                    : 4
 1-bit register                    : 13
# Latches                          : 2
 3-bit latch                       : 1
 6-bit latch                       : 1
# Comparators                      : 11
 6-bit comparator equal            : 1
 6-bit comparator less             : 2
 6-bit comparator greatequal       : 2
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
 26-bit comparator lessequal       : 2
 26-bit comparator greatequal      : 1
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <CT_TIME_0> is constant in block <jtd>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <jt> ...

Optimizing unit <djs> ...

Optimizing unit <jtd> ...

Optimizing unit <fengliwei> ...

Optimizing unit <f05ms> ...

Optimizing unit <f1s> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jt, actual ratio is 23.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     187  out of    768    24%  
 Number of Slice Flip Flops:           126  out of   1536     8%  
 Number of 4 input LUTs:               296  out of   1536    19%  
 Number of bonded IOBs:                 20  out of     96    20%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_24(XLXI_35_I3_0:O)            | NONE(*)(XLXI_9_ashi_2) | 46    |
CLK                                | BUFGP                  | 45    |
XLXN_32(XLXI_36_I3_0:O)            | NONE(*)(XLXI_1_count2_4)| 27    |
XLXI_4__n0021(XLXI_4__n00211:O)    | NONE(*)(XLXI_4_AXS_1)  | 3     |
XLXI_4_CR_STATE_FFd9:Q             | NONE                   | 5     |
-----------------------------------+------------------------+-------+
(*) These 3 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.631ns (Maximum Frequency: 103.831MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 11.936ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\jiaotong/_ngo -uc YJ2.ucf -p
xc2s50-tq144-6 jt.ngc jt.ngd 

Reading NGO file "E:/VHDL/JIAOTONG/jt.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "YJ2.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40164 kilobytes

Writing NGD file "jt.ngd" ...

Writing NGDBUILD log file "jt.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/JIAOTONG/DJS.vhdl in Library work.
Architecture behavioral of Entity djs is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/JTD.vhdl in Library work.
Architecture behavioral of Entity jtd is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/SE41.vhdl in Library work.
Architecture behavioral of Entity se is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/FENLIWEI.vhdl in Library work.
Architecture behavioral of Entity fengliwei is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/f05ms.vhdl in Library work.
Architecture behavioral of Entity f05ms is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/f1s.vhdl in Library work.
Architecture behavioral of Entity f1s is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/xzq.vhdl in Library work.
Architecture behavioral of Entity xzq is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/YMQ1.vhdl in Library work.
Architecture behavioral of Entity ymq1 is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/JT.vhf in Library work.
Architecture behavioral of Entity jt is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <jt> (Architecture <behavioral>).
Entity <jt> analyzed. Unit <jt> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
WARNING:Xst:819 - E:/VHDL/JIAOTONG/DJS.vhdl line 23: The following signals are missing in the process sensitivity list:
   count1, count2.
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <jtd> (Architecture <behavioral>).
Entity <jtd> analyzed. Unit <jtd> generated.

Analyzing Entity <se> (Architecture <behavioral>).
Entity <se> analyzed. Unit <se> generated.

Analyzing Entity <fengliwei> (Architecture <behavioral>).
Entity <fengliwei> analyzed. Unit <fengliwei> generated.

Analyzing Entity <f05ms> (Architecture <behavioral>).
Entity <f05ms> analyzed. Unit <f05ms> generated.

Analyzing Entity <f1s> (Architecture <behavioral>).
Entity <f1s> analyzed. Unit <f1s> generated.

Analyzing Entity <xzq> (Architecture <behavioral>).
WARNING:Xst:819 - E:/VHDL/JIAOTONG/xzq.vhdl line 24: The following signals are missing in the process sensitivity list:
   Q1, Q2, Q3, Q4.
INFO:Xst:1304 - Contents of register <en0> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <en1> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <en2> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <en3> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
Entity <xzq> analyzed. Unit <xzq> generated.

Analyzing Entity <ymq1> (Architecture <behavioral>).
Entity <ymq1> analyzed. Unit <ymq1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ymq1>.
    Related source file is E:/VHDL/JIAOTONG/YMQ1.vhdl.
    Found 16x7-bit ROM for signal <Q>.
    Summary:
	inferred   1 ROM(s).
Unit <ymq1> synthesized.


Synthesizing Unit <xzq>.
    Related source file is E:/VHDL/JIAOTONG/xzq.vhdl.
    Found 4-bit 4-to-1 multiplexer for signal <Q>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <xzq> synthesized.


Synthesizing Unit <f1s>.
    Related source file is E:/VHDL/JIAOTONG/f1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 26-bit comparator lessequal for signal <$n0002>.
    Found 26-bit comparator greatequal for signal <$n0007>.
    Found 26-bit comparator lessequal for signal <$n0008>.
    Found 26-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <f1s> synthesized.


Synthesizing Unit <f05ms>.