__projnav.log

交通灯控制,在A和B方向各用数码管显示剩余的时间.

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file jt.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 937 unrouted;       REAL time: 0 secs 

Phase 2: 883 unrouted;       REAL time: 5 secs 

Phase 3: 201 unrouted;       REAL time: 5 secs 

Phase 4: 0 unrouted;       REAL time: 5 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |   24   |  0.075     |  0.465      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_4_CR_STATE_FFd9    |Low-Skew  |   10   |  0.053     |  4.291      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_8__n0001          |   Local  |    7   |  0.188     |  2.707      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_32          |   Local  |   21   |  0.519     |  2.458      |
+----------------------------+----------+--------+------------+-------------+
|           XLXN_24          |   Local  |   23   |  1.301     |  2.760      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_4__n0021          |   Local  |    2   |  0.000     |  2.561      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 5 secs 

Peak Memory Usage:  65 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file jt.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Apr 06 18:53:43 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module jt . . .
PAR command line: par -w -intstyle ise -ol std -t 1 jt_map.ncd jt.ncd jt.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/FPQ1S.vhdl in Library work.
Entity <fpq1s> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/FPQ2MS.vhdl in Library work.
Entity <fpq05ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/YMQ.vhdl in Library work.
Entity <ymq> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/XZQ41.vhdl in Library work.
Entity <szq41> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/JTD.vhdl in Library work.
Entity <jtd> (Architecture <behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/f1s.vhdl in Library work.
Entity <f1s> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/f05ms.vhdl in Library work.
Entity <f05ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/xzq.vhdl in Library work.
Entity <XZQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file E:/VHDL/JIAOTONG/YMQ1.vhdl in Library work.
Entity <YMQ1> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".

WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about this product,
   please refer to the Evaluation Agreement, which was shipped to you along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact your local
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to: [e-mail]
   Thank You!

=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/VHDL/JIAOTONG/DJS.vhdl in Library work.
Architecture behavioral of Entity djs is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/JTD.vhdl in Library work.
Architecture behavioral of Entity jtd is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/SE41.vhdl in Library work.
Architecture behavioral of Entity se is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/FENLIWEI.vhdl in Library work.
Architecture behavioral of Entity fengliwei is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/f05ms.vhdl in Library work.
Architecture behavioral of Entity f05ms is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/f1s.vhdl in Library work.
Architecture behavioral of Entity f1s is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/xzq.vhdl in Library work.
Architecture behavioral of Entity xzq is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/YMQ1.vhdl in Library work.
Architecture behavioral of Entity ymq1 is up to date.
Compiling vhdl file E:/VHDL/JIAOTONG/JT.vhf in Library work.
Entity <jt> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <jt> (Architecture <behavioral>).
Entity <jt> analyzed. Unit <jt> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
WARNING:Xst:819 - E:/VHDL/JIAOTONG/DJS.vhdl line 23: The following signals are missing in the process sensitivity list:
   count1, count2.
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <jtd> (Architecture <behavioral>).
Entity <jtd> analyzed. Unit <jtd> generated.

Analyzing Entity <se> (Architecture <behavioral>).
Entity <se> analyzed. Unit <se> generated.

Analyzing Entity <fengliwei> (Architecture <behavioral>).
Entity <fengliwei> analyzed. Unit <fengliwei> generated.

Analyzing Entity <f05ms> (Architecture <behavioral>).
Entity <f05ms> analyzed. Unit <f05ms> generated.

Analyzing Entity <f1s> (Architecture <behavioral>).
Entity <f1s> analyzed. Unit <f1s> generated.

Analyzing Entity <xzq> (Architecture <behavioral>).
WARNING:Xst:819 - E:/VHDL/JIAOTONG/xzq.vhdl line 24: The following signals are missing in the process sensitivity list:
   Q1, Q2, Q3, Q4.
INFO:Xst:1304 - Contents of register <en0> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <en1> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <en2> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <en3> in unit <xzq> never changes during circuit operation. The register is replaced by logic.
Entity <xzq> analyzed. Unit <xzq> generated.

Analyzing Entity <ymq1> (Architecture <behavioral>).
Entity <ymq1> analyzed. Unit <ymq1> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <ymq1>.
    Related source file is E:/VHDL/JIAOTONG/YMQ1.vhdl.
    Found 16x7-bit ROM for signal <Q>.
    Summary:
	inferred   1 ROM(s).
Unit <ymq1> synthesized.


Synthesizing Unit <xzq>.
    Related source file is E:/VHDL/JIAOTONG/xzq.vhdl.
    Found 4-bit 4-to-1 multiplexer for signal <Q>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <xzq> synthesized.


Synthesizing Unit <f1s>.
    Related source file is E:/VHDL/JIAOTONG/f1s.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 26-bit comparator lessequal for signal <$n0002>.
    Found 26-bit comparator greatequal for signal <$n0007>.
    Found 26-bit comparator lessequal for signal <$n0008>.
    Found 26-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.