__projnav.log

交通灯控制,在A和B方向各用数码管显示剩余的时间.

    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred   1 Comparator(s).
Unit <jtd> synthesized.


Synthesizing Unit <fpq2ms>.
    Related source file is e:/vhdl/jiaotong/FPQ2MS.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 15-bit comparator lessequal for signal <$n0002>.
    Found 15-bit comparator greatequal for signal <$n0007>.
    Found 15-bit comparator lessequal for signal <$n0008>.
    Found 15-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq2ms> synthesized.


Synthesizing Unit <fpq1s>.
    Related source file is e:/vhdl/jiaotong/FPQ1S.vhdl.
    Found 1-bit tristate buffer for signal <CP>.
    Found 24-bit comparator lessequal for signal <$n0002>.
    Found 24-bit comparator greatequal for signal <$n0007>.
    Found 24-bit comparator lessequal for signal <$n0008>.
    Found 24-bit up counter for signal <a>.
    Found 1-bit register for signal <Mtridata_CP> created at line 28.
    Found 1-bit register for signal <Mtrien_CP> created at line 28.
    Summary:
	inferred   1 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   1 Tristate(s).
Unit <fpq1s> synthesized.


Synthesizing Unit <djs>.
    Related source file is e:/vhdl/jiaotong/DJS.vhdl.
    Found 6-bit subtractor for signal <$n0010>.
    Found 6-bit subtractor for signal <$n0011>.
    Found 6-bit register for signal <count1>.
    Found 6-bit register for signal <count2>.
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
Unit <djs> synthesized.


Synthesizing Unit <jt>.
    Related source file is e:/vhdl/jiaotong/JT.vhf.
Unit <jt> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CR_STATE> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 2
 6-bit subtractor                  : 2
# Counters                         : 10
 6-bit up counter                  : 3
 24-bit up counter                 : 1
 15-bit up counter                 : 1
 4-bit up counter                  : 4
 2-bit up counter                  : 1
# Registers                        : 19
 6-bit register                    : 2
 1-bit register                    : 13
 4-bit register                    : 4
# Latches                          : 3
 3-bit latch                       : 1
 6-bit latch                       : 1
 7-bit latch                       : 1
# Comparators                      : 11
 24-bit comparator lessequal       : 2
 24-bit comparator greatequal      : 1
 15-bit comparator lessequal       : 2
 15-bit comparator greatequal      : 1
 6-bit comparator equal            : 1
 6-bit comparator less             : 2
 6-bit comparator greatequal       : 2
# Multiplexers                     : 1
 4-bit 4-to-1 multiplexer          : 1
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <CT_TIME_0> is constant in block <jtd>.
INFO:Xst:1907 - HDL ADVISOR - Internal tri-states were detected in your design. You may improve design performance and/or area by replacing them by logic using the 'Convert Tristates to Logic' option.

Optimizing unit <jt> ...

Optimizing unit <djs> ...

Optimizing unit <fpq1s> ...

Optimizing unit <fpq2ms> ...

Optimizing unit <jtd> ...

Optimizing unit <ymq> ...

Optimizing unit <fengliwei> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block jt, actual ratio is 22.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-6 

 Number of Slices:                     186  out of    768    24%  
 Number of Slice Flip Flops:           131  out of   1536     8%  
 Number of 4 input LUTs:               293  out of   1536    19%  
 Number of bonded IOBs:                 20  out of     96    20%  
 Number of TBUFs:                        2  out of    768     0%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXN_32(XLXI_2_I3_0:O)             | NONE(*)(XLXI_1_count1_3)| 27    |
XLXN_24(XLXI_3_I3_0:O)             | NONE(*)(XLXI_9_comb1_3)| 46    |
CLK                                | BUFGP                  | 43    |
XLXI_4__n0021(XLXI_4__n00211:O)    | NONE(*)(XLXI_4_AXS_0)  | 3     |
XLXI_4_CR_STATE_FFd9:Q             | NONE                   | 5     |
XLXI_8__n0001(XLXI_8__n00011:O)    | NONE(*)(XLXI_8_Q_3)    | 7     |
-----------------------------------+------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.541ns (Maximum Frequency: 104.811MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 10.766ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\jiaotong/_ngo -uc YJ.ucf -p
xc2s50-tq144-6 jt.ngc jt.ngd 

Reading NGO file "e:/vhdl/jiaotong/jt.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "YJ.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 53068 kilobytes

Writing NGD file "jt.ngd" ...

Writing NGDBUILD log file "jt.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd e:\vhdl\jiaotong/_ngo -uc YJ.ucf -p
xc2s50-tq144-6 jt.ngc jt.ngd 

Reading NGO file "e:/vhdl/jiaotong/jt.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "YJ.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 55052 kilobytes

Writing NGD file "jt.ngd" ...

Writing NGDBUILD log file "jt.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Total Number Slice Registers:     124 out of  1,536    8%
    Number used as Flip Flops:                    116
    Number used as Latches:                         8
  Number of 4 input LUTs:           208 out of  1,536   13%
Logic Distribution:
    Number of occupied Slices:                         167 out of    768   21%
    Number of Slices containing only related logic:    167 out of    167  100%
    Number of Slices containing unrelated logic:         0 out of    167    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          290 out of  1,536   18%
      Number used as logic:                       208
      Number used as a route-thru:                 82
   Number of bonded IOBs:            20 out of     92   21%
      IOB Latches:                                  7
   Number of Tbufs:                   2 out of    832    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  3,004
Additional JTAG gate count for IOBs:  1,008
Peak Memory Usage:  74 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "jt_map.mrp" for details.
Completed process "Map".

Mapping Module jt . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-6 -cm area -pr b -k 4 -c 100 -tx off -o jt_map.ncd jt.ngd jt.pcf
Mapping Module jt: DONE



Started process "Place & Route".





Constraints file: jt.pcf

Loading device database for application Par from file "jt_map.ncd".
   "jt" is an NCD, version 2.38, device xc2s50, package tq144, speed -6
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            20 out of 92     21%
      Number of LOCed External IOBs   20 out of 20    100%

   Number of SLICEs                  167 out of 768    21%

   Number of GCLKs                     1 out of 4      25%
   Number of TBUFs                     2 out of 832     1%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989ca4) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.......................
Phase 5.8 (Checksum:9cf4db) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs