__projnav.log

交通灯控制,在A和B方向各用数码管显示剩余的时间.

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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/DJS.vhdl in Library work.
Entity <DJS> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/FPQ1S.vhdl in Library work.
Entity <fpq1s> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



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-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/FPQ2MS.vhdl in Library work.
Entity <fpq2ms> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/JTD.vhdl in Library work.
Entity <JTD> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/SE41.vhdl in Library work.
Entity <SE> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/XZQ41.vhdl in Library work.
ERROR:HDLParsers:3010 - e:/vhdl/jiaotong/XZQ41.vhdl Line 22. Entity SZQ2 does
   not exist.
ERROR:HDLParsers:3312 - e:/vhdl/jiaotong/XZQ41.vhdl Line 24. Undefined symbol
   'S'.
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/XZQ41.vhdl Line 24. S: Undefined symbol
   (last report in this block)
ERROR:HDLParsers:3312 - e:/vhdl/jiaotong/XZQ41.vhdl Line 27. Undefined symbol
   'Q'.
ERROR:HDLParsers:3312 - e:/vhdl/jiaotong/XZQ41.vhdl Line 27. Undefined symbol
   'Q1'.
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/XZQ41.vhdl Line 27. Q1: Undefined
   symbol (last report in this block)
ERROR:HDLParsers:3312 - e:/vhdl/jiaotong/XZQ41.vhdl Line 28. Undefined symbol
   'WX'.
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/XZQ41.vhdl Line 30. Q: Undefined symbol
   (last report in this block)
ERROR:HDLParsers:3312 - e:/vhdl/jiaotong/XZQ41.vhdl Line 30. Undefined symbol
   'Q2'.
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/XZQ41.vhdl Line 30. Q2: Undefined
   symbol (last report in this block)
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/XZQ41.vhdl Line 31. WX: Undefined
   symbol (last report in this block)
ERROR:HDLParsers:164 - e:/vhdl/jiaotong/XZQ41.vhdl Line 32. parse error,
   unexpected TICK
ERROR:HDLParsers:3312 - e:/vhdl/jiaotong/XZQ41.vhdl Line 36. Undefined symbol
   'Q4'.
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/XZQ41.vhdl Line 36. Q4: Undefined
   symbol (last report in this block)
WARNING:HDLParsers:1406 - e:/vhdl/jiaotong/XZQ41.vhdl Line 24. No sensitivity
   list and no wait in the process
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/XZQ41.vhdl in Library work.
ERROR:HDLParsers:164 - e:/vhdl/jiaotong/XZQ41.vhdl Line 32. parse error,
   unexpected TICK
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/XZQ41.vhdl in Library work.
Entity <SZQ41> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/YMQ.vhdl in Library work.
Entity <YMQ> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/FENLIWEI.vhdl in Library work.
ERROR:HDLParsers:3313 - e:/vhdl/jiaotong/FENLIWEI.vhdl Line 46. Undefined symbol
   'clr'.  Should it be: cr?
ERROR:HDLParsers:1209 - e:/vhdl/jiaotong/FENLIWEI.vhdl Line 46. clr: Undefined
   symbol (last report in this block)
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Create Schematic Symbol".

Compiling vhdl file e:/vhdl/jiaotong/FENLIWEI.vhdl in Library work.
Entity <FENGLIWEI> (Architecture <Behavioral>) compiled.
tdtfi(vhdl) completed successfully.


Release 6.2i - spl2sym G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
Completed process "Create Schematic Symbol".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "View VHDL Functional Model".

Release 6.2i - sch2vhdl G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
DRC Check completed: No Error found.
Vhdl netlist file generated.
Completed process "View VHDL Functional Model".





Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file e:/vhdl/jiaotong/DJS.vhdl in Library work.
Architecture behavioral of Entity djs is up to date.
Compiling vhdl file e:/vhdl/jiaotong/FPQ1S.vhdl in Library work.
Architecture behavioral of Entity fpq1s is up to date.
Compiling vhdl file e:/vhdl/jiaotong/FPQ2MS.vhdl in Library work.
Architecture behavioral of Entity fpq2ms is up to date.
Compiling vhdl file e:/vhdl/jiaotong/JTD.vhdl in Library work.
Architecture behavioral of Entity jtd is up to date.
Compiling vhdl file e:/vhdl/jiaotong/SE41.vhdl in Library work.
Architecture behavioral of Entity se is up to date.
Compiling vhdl file e:/vhdl/jiaotong/XZQ41.vhdl in Library work.
Architecture behavioral of Entity szq41 is up to date.
Compiling vhdl file e:/vhdl/jiaotong/YMQ.vhdl in Library work.
Architecture behavioral of Entity ymq is up to date.
Compiling vhdl file e:/vhdl/jiaotong/FENLIWEI.vhdl in Library work.
Architecture behavioral of Entity fengliwei is up to date.
Compiling vhdl file e:/vhdl/jiaotong/JT.vhf in Library work.
Entity <jt> (Architecture <BEHAVIORAL>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <jt> (Architecture <BEHAVIORAL>).
Entity <jt> analyzed. Unit <jt> generated.

Analyzing Entity <djs> (Architecture <behavioral>).
WARNING:Xst:819 - e:/vhdl/jiaotong/DJS.vhdl line 23: The following signals are missing in the process sensitivity list:
   count1, count2.
Entity <djs> analyzed. Unit <djs> generated.

Analyzing Entity <fpq1s> (Architecture <behavioral>).
Entity <fpq1s> analyzed. Unit <fpq1s> generated.

Analyzing Entity <fpq2ms> (Architecture <behavioral>).
Entity <fpq2ms> analyzed. Unit <fpq2ms> generated.

Analyzing Entity <jtd> (Architecture <behavioral>).
Entity <jtd> analyzed. Unit <jtd> generated.

Analyzing Entity <se> (Architecture <behavioral>).
Entity <se> analyzed. Unit <se> generated.

Analyzing Entity <szq41> (Architecture <behavioral>).
WARNING:Xst:819 - e:/vhdl/jiaotong/XZQ41.vhdl line 24: The following signals are missing in the process sensitivity list:
   Q1, Q2, Q3, Q4.
Entity <szq41> analyzed. Unit <szq41> generated.

Analyzing Entity <ymq> (Architecture <behavioral>).
Entity <ymq> analyzed. Unit <ymq> generated.

Analyzing Entity <fengliwei> (Architecture <behavioral>).
Entity <fengliwei> analyzed. Unit <fengliwei> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <fengliwei>.
    Related source file is e:/vhdl/jiaotong/FENLIWEI.vhdl.
    Found 4-bit register for signal <ashi>.
    Found 4-bit register for signal <age>.
    Found 4-bit register for signal <bshi>.
    Found 4-bit register for signal <bge>.
    Found 6-bit comparator greatequal for signal <$n0012> created at line 27.
    Found 6-bit comparator less for signal <$n0013> created at line 27.
    Found 6-bit comparator greatequal for signal <$n0014> created at line 51.
    Found 6-bit comparator less for signal <$n0015> created at line 51.
    Found 6-bit up counter for signal <comb1>.
    Found 4-bit up counter for signal <comb1a>.
    Found 4-bit up counter for signal <comb1b>.
    Found 6-bit up counter for signal <comb2>.
    Found 4-bit up counter for signal <comb2a>.
    Found 4-bit up counter for signal <comb2b>.
    Summary:
	inferred   6 Counter(s).
	inferred  16 D-type flip-flop(s).
	inferred   4 Comparator(s).
Unit <fengliwei> synthesized.


Synthesizing Unit <ymq>.
    Related source file is e:/vhdl/jiaotong/YMQ.vhdl.
WARNING:Xst:737 - Found 7-bit latch for signal <Q>.
Unit <ymq> synthesized.


Synthesizing Unit <szq41>.
    Related source file is e:/vhdl/jiaotong/XZQ41.vhdl.
    Found 4-bit 4-to-1 multiplexer for signal <Q>.
    Summary:
	inferred   4 Multiplexer(s).
Unit <szq41> synthesized.


Synthesizing Unit <se>.
    Related source file is e:/vhdl/jiaotong/SE41.vhdl.
    Found 2-bit up counter for signal <b>.
    Summary:
	inferred   1 Counter(s).
Unit <se> synthesized.


Synthesizing Unit <jtd>.
    Related source file is e:/vhdl/jiaotong/JTD.vhdl.
    Found finite state machine <FSM_0> for signal <CR_STATE>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 9                                              |
    | Inputs             | 0                                              |
    | Outputs            | 13                                             |
    | Clock              | clk (rising_edge)                              |
    | Clock enable       | $n0001 (positive)                              |
    | Reset              | rst (positive)                                 |
    | Reset type         | asynchronous                                   |
    | Reset State        | rr                                             |
    | Power Up State     | rr                                             |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
WARNING:Xst:737 - Found 6-bit latch for signal <CT_TIME>.
WARNING:Xst:737 - Found 3-bit latch for signal <AXS>.
    Found 6-bit comparator equal for signal <$n0001> created at line 45.
    Found 6-bit up counter for signal <COUNT>.