📄 fpq05ms.twr
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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
C:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml fpq05ms fpq05ms.ncd -o
fpq05ms.twr fpq05ms.pcf
Design file: fpq05ms.ncd
Physical constraint file: fpq05ms.pcf
Device,speed: xc2s50,-5 (PRODUCTION 1.27 2003-12-13)
Report level: error report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock CLK to Pad
------------+------------+------------------+--------+
| clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+
CP | 8.120(R)|CLK_BUFGP | 0.000|
------------+------------+------------------+--------+
Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK | 8.372| | | |
---------------+---------+---------+---------+---------+
Analysis completed Tue Apr 10 20:32:38 2007
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Peak Memory Usage: 45 MB
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