fpq05ms.par

交通灯控制,在A和B方向各用数码管显示剩余的时间.

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

0599F88D4B5146E::  Tue Apr 10 20:32:36 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 fpq05ms_map.ncd
fpq05ms.ncd fpq05ms.pcf 


Constraints file: fpq05ms.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "fpq05ms_map.ncd".
   "fpq05ms" is an NCD, version 2.38, device xc2s50, package tq144, speed -5
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs             1 out of 92      1%
      Number of LOCed External IOBs    0 out of 1       0%

   Number of SLICEs                   15 out of 768     1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896b6) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98cdde) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file fpq05ms.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 90 unrouted;       REAL time: 0 secs 

Phase 2: 81 unrouted;       REAL time: 0 secs 

Phase 3: 15 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         CLK_BUFGP          |  Global  |    9   |  0.180     |  0.635      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 129


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.016
   The MAXIMUM PIN DELAY IS:                               2.083
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.363

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          42          46           2           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 0 secs 
Total CPU time to PAR completion: 0 secs 

Peak Memory Usage:  47 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file fpq05ms.ncd.


PAR done.