se41.vhdl

来自「交通灯控制,在A和B方向各用数码管显示剩余的时间.」· VHDL 代码 · 共 32 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SE is
    Port ( clk : in std_logic;
           sell : out std_logic_vector(1 downto 0));
end SE;

architecture Behavioral of SE is

begin
    process(clk)
    variable b:std_logic_vector(1 downto 0);
    begin
       if(clk'event and clk='1')then
	     if(b="11")then
		   b:="00";
		else
		   b:=b+1;
		end if;
	   end if;
	   sell<=b;
    end process; 	    
end Behavioral;