coregen.log

在LCD上显示事先就输入好的字符,可以任意改变的

# Xilinx CORE Generator 6.2i
# User = dragonlee
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in F:\dragon\VHDL\myboard\ok\lcd1621\coregen.log
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=F:\dragon\VHDL\myboard\ok\lcd1621
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=F:\dragon\VHDL\myboard\ok\lcd1621
SETPROJECT .
Set current Project to F:\dragon\VHDL\myboard\ok\lcd1621
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1046
XIPCPJSENDCORES spartan2