__projnav.log

在LCD上显示事先就输入好的字符,可以任意改变的

Analyzing Entity <lcd162> (Architecture <BEHAVIORAL>).
INFO:Xst:1739 - HDL ADVISOR - f:/dragon/vhdl/myboard/lcd162/lcd162.vhf line 163: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <lcd162> analyzed. Unit <lcd162> generated.

Analyzing Entity <lcd> (Architecture <behavioral>).
Entity <lcd> analyzed. Unit <lcd> generated.

Analyzing Entity <char_ram> (Architecture <fun>).
Entity <char_ram> analyzed. Unit <char_ram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <char_ram>.
    Related source file is f:/dragon/vhdl/myboard/lcd162/lcd.vhdl.
    Found 32x8-bit ROM for signal <$n0000>.
    Summary:
	inferred   1 ROM(s).
Unit <char_ram> synthesized.


Synthesizing Unit <lcd>.
    Related source file is f:/dragon/vhdl/myboard/lcd162/lcd.vhdl.
    Using one-hot encoding for signal <state>.
    Found 1-bit register for signal <lcd_e>.
    Found 8-bit tristate buffer for signal <data>.
    Found 4-bit comparator less for signal <$n0008> created at line 308.
    Found 7-bit comparator less for signal <$n0010> created at line 337.
    Found 6-bit subtractor for signal <$n0022> created at line 285.
    Found 3-bit adder for signal <$n0023> created at line 285.
    Found 6-bit subtractor for signal <$n0024> created at line 285.
    Found 3-bit adder for signal <$n0025> created at line 285.
    Found 7-bit comparator less for signal <$n0032> created at line 285.
    Found 7-bit comparator greater for signal <$n0033> created at line 285.
    Found 7-bit comparator less for signal <$n0034> created at line 285.
    Found 7-bit comparator greater for signal <$n0035> created at line 285.
    Found 7-bit adder for signal <$n0036> created at line 340.
    Found 4-bit adder for signal <$n0039> created at line 309.
    Found 1-bit register for signal <clk_int>.
    Found 19-bit up counter for signal <clkcnt>.
    Found 1-bit register for signal <clkdiv>.
    Found 7-bit register for signal <counter>.
    Found 4-bit register for signal <div_counter>.
    Found 1-bit register for signal <flag>.
    Found 11-bit register for signal <state>.
    Summary:
	inferred   1 Counter(s).
	inferred  15 D-type flip-flop(s).
	inferred   6 Adder/Subtracter(s).
	inferred   6 Comparator(s).
	inferred   8 Tristate(s).
Unit <lcd> synthesized.


Synthesizing Unit <lcd162>.
    Related source file is f:/dragon/vhdl/myboard/lcd162/lcd162.vhf.
Unit <lcd162> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 32x8-bit ROM                      : 1
# Adders/Subtractors               : 6
 4-bit adder                       : 1
 7-bit adder                       : 1
 6-bit subtractor                  : 2
 3-bit adder                       : 2
# Counters                         : 1
 19-bit up counter                 : 1
# Registers                        : 7
 4-bit register                    : 1
 1-bit register                    : 4
 7-bit register                    : 1
 11-bit register                   : 1
# Comparators                      : 6
 7-bit comparator greater          : 2
 7-bit comparator less             : 3
 4-bit comparator less             : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <XLXI_1_state_10> (without init value) is constant in block <lcd162>.
WARNING:Xst:1710 - FF/Latch  <XLXI_1_state_2> (without init value) is constant in block <lcd162>.
WARNING:Xst:1710 - FF/Latch  <XLXI_1_state_7> (without init value) is constant in block <lcd162>.

Optimizing unit <lcd162> ...

Optimizing unit <char_ram> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx6.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd162, actual ratio is 11.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      81  out of    768    10%  
 Number of Slice Flip Flops:            42  out of   1536     2%  
 Number of 4 input LUTs:               139  out of   1536     9%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_1_clk_int:Q                   | NONE                   | 20    |
clk                                | BUFGP                  | 19    |
XLXI_1_tc_clkcnt(XLXI_1__n001485:O)| NONE(*)(XLXI_1_clkdiv) | 1     |
XLXI_1_clkdiv:Q                    | NONE                   | 2     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 12.130ns (Maximum Frequency: 82.440MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 29.659ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\dragon\vhdl\myboard\lcd162/_ngo -uc
yjiao.ucf -p xc2s50-tq144-5 lcd162.ngc lcd162.ngd 

Reading NGO file "f:/dragon/vhdl/myboard/lcd162/lcd162.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yjiao.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 40164 kilobytes

Writing NGD file "lcd162.ngd" ...

Writing NGDBUILD log file "lcd162.bld"...

NGDBUILD done.
Completed process "Translate".



Project Navigator Auto-Make Log File
-------------------------------------


Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd f:\dragon\vhdl\myboard\lcd162/_ngo -uc
yjiao.ucf -p xc2s50-tq144-5 lcd162.ngc lcd162.ngd 

Reading NGO file "f:/dragon/vhdl/myboard/lcd162/lcd162.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "yjiao.ucf" ...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 41188 kilobytes

Writing NGD file "lcd162.ngd" ...

Writing NGDBUILD log file "lcd162.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50tq144-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:        42 out of  1,536    2%
  Number of 4 input LUTs:           120 out of  1,536    7%
Logic Distribution:
    Number of occupied Slices:                          78 out of    768   10%
    Number of Slices containing only related logic:     78 out of     78  100%
    Number of Slices containing unrelated logic:         0 out of     78    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          139 out of  1,536    9%
      Number used as logic:                       120
      Number used as a route-thru:                 19
   Number of bonded IOBs:            12 out of     92   13%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  1,335
Additional JTAG gate count for IOBs:  624
Peak Memory Usage:  59 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "lcd162_map.mrp" for details.
Completed process "Map".

Mapping Module lcd162 . . .
MAP command line:
map -intstyle ise -p xc2s50-tq144-5 -cm area -pr b -k 4 -c 100 -tx off -o lcd162_map.ncd lcd162.ngd lcd162.pcf
Mapping Module lcd162: DONE



Started process "Place & Route".





Constraints file: lcd162.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 60
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "lcd162_map.ncd".
   "lcd162" is an NCD, version 2.38, device xc2s50, package tq144, speed -5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx6.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            12 out of 92     13%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of SLICEs                   78 out of 768    10%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9898d7) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8