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Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file f:/dragon/vhdl/myboard/lcd162/lcd.vhdl in Library work.Entity <char_ram> (Architecture <fun>) compiled.Entity <lcd> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <lcd> (Architecture <Behavioral>).INFO:Xst:1739 - HDL ADVISOR - f:/dragon/vhdl/myboard/lcd162/lcd.vhdl line 163: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.Entity <lcd> analyzed. Unit <lcd> generated.Analyzing Entity <char_ram> (Architecture <fun>).Entity <char_ram> analyzed. Unit <char_ram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <char_ram>. Related source file is f:/dragon/vhdl/myboard/lcd162/lcd.vhdl. Found 32x8-bit ROM for signal <$n0000>. Summary: inferred 1 ROM(s).Unit <char_ram> synthesized.Synthesizing Unit <lcd>. Related source file is f:/dragon/vhdl/myboard/lcd162/lcd.vhdl. Using one-hot encoding for signal <state>. Found 1-bit register for signal <lcd_e>. Found 8-bit tristate buffer for signal <data>. Found 4-bit comparator less for signal <$n0008> created at line 308. Found 7-bit comparator less for signal <$n0010> created at line 337. Found 6-bit subtractor for signal <$n0022> created at line 285. Found 3-bit adder for signal <$n0023> created at line 285. Found 6-bit subtractor for signal <$n0024> created at line 285. Found 3-bit adder for signal <$n0025> created at line 285. Found 7-bit comparator less for signal <$n0032> created at line 285. Found 7-bit comparator greater for signal <$n0033> created at line 285. Found 7-bit comparator less for signal <$n0034> created at line 285. Found 7-bit comparator greater for signal <$n0035> created at line 285. Found 7-bit adder for signal <$n0036> created at line 340. Found 4-bit adder for signal <$n0039> created at line 309. Found 1-bit register for signal <clk_int>. Found 19-bit up counter for signal <clkcnt>. Found 1-bit register for signal <clkdiv>. Found 7-bit register for signal <counter>. Found 4-bit register for signal <div_counter>. Found 1-bit register for signal <flag>. Found 11-bit register for signal <state>. Summary: inferred 1 Counter(s). inferred 15 D-type flip-flop(s). inferred 6 Adder/Subtracter(s). inferred 6 Comparator(s). inferred 8 Tristate(s).Unit <lcd> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 32x8-bit ROM : 1# Adders/Subtractors : 6 4-bit adder : 1 7-bit adder : 1 6-bit subtractor : 2 3-bit adder : 2# Counters : 1 19-bit up counter : 1# Registers : 7 4-bit register : 1 1-bit register : 4 7-bit register : 1 11-bit register : 1# Comparators : 6 7-bit comparator greater : 2 7-bit comparator less : 3 4-bit comparator less : 1# Tristates : 1 8-bit tristate buffer : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================WARNING:Xst:1710 - FF/Latch <state_10> (without init value) is constant in block <lcd>.WARNING:Xst:1710 - FF/Latch <state_2> (without init value) is constant in block <lcd>.WARNING:Xst:1710 - FF/Latch <state_7> (without init value) is constant in block <lcd>.Optimizing unit <lcd> ...Optimizing unit <char_ram> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx6.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block lcd, actual ratio is 11.FlipFlop state_9 has been replicated 1 time(s)=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-5 Number of Slices: 83 out of 768 10% Number of Slice Flip Flops: 43 out of 1536 2% Number of 4 input LUTs: 142 out of 1536 9% Number of bonded IOBs: 12 out of 96 12% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk_int:Q | NONE | 21 |clk | BUFGP | 19 |tc_clkcnt(_n001485:O) | NONE(*)(clkdiv) | 1 |clkdiv:Q | NONE | 2 |-----------------------------------+------------------------+-------+(*) This 1 clock signal(s) are generated by combinatorial logic,and XST is not able to identify which are the primary clock signals.Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.Timing Summary:---------------Speed Grade: -5 Minimum period: 12.240ns (Maximum Frequency: 81.699MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 29.659ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Create Schematic Symbol".Compiling vhdl file f:/dragon/vhdl/myboard/lcd162/lcd.vhdl in Library work.Entity <char_ram> (Architecture <fun>) compiled.Entity <lcd> (Architecture <behavioral>) compiled.tdtfi(vhdl) completed successfully.
Release 6.2i - spl2sym G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.Completed process "Create Schematic Symbol".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file f:/dragon/vhdl/myboard/lcd162/lcd.vhdl in Library work.Architecture fun of Entity char_ram is up to date.Architecture behavioral of Entity lcd is up to date.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <char_ram> (Architecture <fun>).Entity <char_ram> analyzed. Unit <char_ram> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <char_ram>. Related source file is f:/dragon/vhdl/myboard/lcd162/lcd.vhdl. Found 32x8-bit ROM for signal <$n0000>. Summary: inferred 1 ROM(s).Unit <char_ram> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 32x8-bit ROM : 1==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <char_ram> ...Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx6.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block char_ram, actual ratio is 1.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s50tq144-5 Number of Slices: 10 out of 768 1% Number of 4 input LUTs: 19 out of 1536 1% Number of bonded IOBs: 14 out of 96 14% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 12.862ns=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "View VHDL Functional Model".Release 6.2i - sch2vhdl G.28Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.DRC Check completed: No Error found.Vhdl netlist file generated.Completed process "View VHDL Functional Model".
Started process "Synthesize".WARNING:Xst:1530 - You are using an evaluation version of Xilinx Software. In 60 days, this program will not operate. For more information about this product, please refer to the Evaluation Agreement, which was shipped to you along with the Evaluation CDs. To purchase an annual license for this software, please contact your local Field Applications Engineer (FAE) or salesperson. If you have any questions, or if we can assist in any way, please send an email to: eval@xilinx.com Thank You!=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file f:/dragon/vhdl/myboard/lcd162/lcd.vhdl in Library work.Architecture fun of Entity char_ram is up to date.Architecture behavioral of Entity lcd is up to date.Compiling vhdl file f:/dragon/vhdl/myboard/lcd162/lcd162.vhf in Library work.Entity <lcd162> (Architecture <BEHAVIORAL>) compiled.=========================================================================* HDL Analysis *=========================================================================⌨️ 快捷键说明
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