lcd2.syr

在LCD上显示事先就输入好的字符,可以任意改变的

Cell Usage :
# BELS                             : 204
#      GND                         : 1
#      LUT1                        : 15
#      LUT2                        : 7
#      LUT2_L                      : 1
#      LUT3                        : 8
#      LUT3_L                      : 4
#      LUT4                        : 65
#      LUT4_D                      : 3
#      LUT4_L                      : 22
#      MUXCY                       : 28
#      MUXF5                       : 14
#      MUXF6                       : 7
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 41
#      FDC                         : 15
#      FDC_1                       : 1
#      FDCE                        : 5
#      FDCPE                       : 19
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 3
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      71  out of    768     9%  
 Number of Slice Flip Flops:            41  out of   1536     2%  
 Number of 4 input LUTs:               125  out of   1536     8%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_int:Q                          | NONE                   | 19    |
clk                                | BUFGP                  | 19    |
tc_clkcnt(_n001285:O)              | NONE(*)(clkdiv)        | 1     |
clkdiv:Q                           | NONE                   | 2     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.268ns (Maximum Frequency: 88.747MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 26.820ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk_int:Q'
Delay:               9.151ns (Levels of Logic = 2)
  Source:            state_9 (FF)
  Destination:       counter_0 (FF)
  Source Clock:      clk_int:Q rising
  Destination Clock: clk_int:Q rising

  Data Path: state_9 to counter_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             20   1.292   3.200  state_9 (state_9)
     LUT4_D:I0->O         14   0.653   2.600  Ker30921 (N3094)
     LUT4_L:I3->LO         1   0.653   0.000  _n0017<4>1 (_n0017<4>)
     FDC:D                     0.753          counter_4
    ----------------------------------------
    Total                      9.151ns (3.351ns logic, 5.800ns route)
                                       (36.6% logic, 63.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               11.268ns (Levels of Logic = 19)
  Source:            clkcnt_7 (FF)
  Destination:       clkcnt_18 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: clkcnt_7 to clkcnt_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   1.292   1.340  clkcnt_7 (clkcnt_7)
     LUT4:I0->O            2   0.653   1.340  _n001219 (CHOICE49)
     LUT2:I1->O           14   0.653   2.600  _n001220 (CHOICE50)
     LUT4_L:I0->LO         1   0.653   0.000  clkcnt_inst_lut3_31 (clkcnt_inst_lut3_3)
     MUXCY:S->O            1   0.784   0.000  clkcnt_inst_cy_4 (clkcnt_inst_cy_4)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_5 (clkcnt_inst_cy_5)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_6 (clkcnt_inst_cy_6)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_7 (clkcnt_inst_cy_7)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_8 (clkcnt_inst_cy_8)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_9 (clkcnt_inst_cy_9)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_10 (clkcnt_inst_cy_10)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_11 (clkcnt_inst_cy_11)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_12 (clkcnt_inst_cy_12)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_13 (clkcnt_inst_cy_13)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_14 (clkcnt_inst_cy_14)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_15 (clkcnt_inst_cy_15)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_16 (clkcnt_inst_cy_16)
     MUXCY:CI->O           1   0.050   0.000  clkcnt_inst_cy_17 (clkcnt_inst_cy_17)
     MUXCY:CI->O           0   0.050   0.000  clkcnt_inst_cy_18 (clkcnt_inst_cy_18)
     XORCY:CI->O           1   0.500   0.000  clkcnt_inst_sum_18 (clkcnt_inst_sum_18)
     FDCPE:D                   0.753          clkcnt_18
    ----------------------------------------
    Total                     11.268ns (5.988ns logic, 5.280ns route)
                                       (53.1% logic, 46.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock '_n001285:O'
Delay:               4.178ns (Levels of Logic = 1)
  Source:            clkdiv (FF)
  Destination:       clkdiv (FF)
  Source Clock:      _n001285:O rising
  Destination Clock: _n001285:O rising

  Data Path: clkdiv to clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   1.292   1.480  clkdiv (clkdiv)
     LUT1:I0->O            1   0.653   0.000  _n00391 (_n0039)
     FDC:D                     0.753          clkdiv
    ----------------------------------------
    Total                      4.178ns (2.698ns logic, 1.480ns route)
                                       (64.6% logic, 35.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clkdiv:Q'
Delay:               5.898ns (Levels of Logic = 1)
  Source:            clk_int (FF)
  Destination:       clk_int (FF)
  Source Clock:      clkdiv:Q rising
  Destination Clock: clkdiv:Q rising

  Data Path: clk_int to clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             20   1.292   3.200  clk_int (clk_int)
     LUT1:I0->O            1   0.653   0.000  _n00401 (_n0040)
     FDC:D                     0.753          clk_int
    ----------------------------------------
    Total                      5.898ns (2.698ns logic, 3.200ns route)
                                       (45.7% logic, 54.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clkdiv:Q'
Offset:              8.189ns (Levels of Logic = 1)
  Source:            lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      clkdiv:Q falling

  Data Path: lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  lcd_e (lcd_e_OBUF)
     OBUF:I->O                 5.557          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      8.189ns (6.849ns logic, 1.340ns route)
                                       (83.6% logic, 16.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_int:Q'
Offset:              26.820ns (Levels of Logic = 8)
  Source:            state_9 (FF)
  Destination:       data<3> (PAD)
  Source Clock:      clk_int:Q rising

  Data Path: state_9 to data<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             20   1.292   3.200  state_9 (state_9)
     LUT4_D:I0->O         14   0.653   2.600  Ker30921 (N3094)
     LUT2:I0->O           33   0.653   3.850  char_addr<0>1 (char_addr<0>)
     LUT4:I0->O            1   0.653   1.150  aa_Mrom_data_inst_mux_f6_7_SW1 (N3788)
     LUT4:I2->O            1   0.653   1.150  aa_Mrom_data_inst_mux_f6_7 (aa_Mrom_data__net27)
     LUT4:I2->O            1   0.653   1.150  aa_Mrom_data_inst_lut3_221 (data_in<3>)
     LUT3:I2->O            1   0.653   1.150  _n0022<3>_SW0 (N3324)
     LUT4:I3->O            1   0.653   1.150  _n0022<3> (data_3_OBUFT)
     OBUFT:I->O                5.557          data_3_OBUFT (data<3>)
    ----------------------------------------
    Total                     26.820ns (11.420ns logic, 15.400ns route)
                                       (42.6% logic, 57.4% route)

=========================================================================
CPU : 6.94 / 8.28 s | Elapsed : 7.00 / 8.00 s
 
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Total memory usage is 58476 kilobytes