lcd162.par

在LCD上显示事先就输入好的字符,可以任意改变的

Release 6.2i Par G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

ZSX::  Tue Apr 17 11:12:42 2007


C:/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1 lcd162_map.ncd
lcd162.ncd lcd162.pcf 


Constraints file: lcd162.pcf
WARNING:Par:331 - You are using an evaluation version of Xilinx Software. In 53
   days, this program will not operate. For more information about thisproduct,
   please refer to the Evaluation Agreement, which was shipped toyou along with
   the Evaluation CDs.
   To purchase an annual license for this software, please contact yourlocal
   Field Applications Engineer (FAE) or salesperson. If you have any questions,
   or if we can assist in any way, please send an email to:[e-mail]
   Thank You!

Loading device database for application Par from file "lcd162_map.ncd".
   "lcd162" is an NCD, version 2.38, device xc2s50, package tq144, speed -5
Loading device for application Par from file 'v50.nph' in environment C:/Xilinx.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolved that IOB <d<7>> must be placed at site P10.
Resolved that IOB <lcd_rw> must be placed at site P20.
Resolved that GCLKIOB <clk> must be placed at site P18.
Resolved that IOB <lcd_e> must be placed at site P19.
Resolved that IOB <d<0>> must be placed at site P140.
Resolved that IOB <d<1>> must be placed at site P139.
Resolved that IOB <d<2>> must be placed at site P141.
Resolved that IOB <d<3>> must be placed at site P4.
Resolved that IOB <rst> must be placed at site P3.
Resolved that IOB <d<4>> must be placed at site P5.
Resolved that IOB <d<5>> must be placed at site P6.
Resolved that IOB <lcd_rs> must be placed at site P21.
Resolved that IOB <d<6>> must be placed at site P7.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            12 out of 92     13%
      Number of LOCed External IOBs   12 out of 12    100%

   Number of SLICEs                   72 out of 768     9%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98988f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
....
Phase 5.8 (Checksum:99a326) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file lcd162.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 542 unrouted;       REAL time: 0 secs 

Phase 2: 521 unrouted;       REAL time: 0 secs 

Phase 3: 156 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   10   |  0.000     |  0.651      |
+----------------------------+----------+--------+------------+-------------+
|    XLXI_2_clk_int          |Low-Skew  |   12   |  0.304     |  4.898      |
+----------------------------+----------+--------+------------+-------------+
|     XLXI_2_clkdiv          |Low-Skew  |    3   |  0.033     |  4.750      |
+----------------------------+----------+--------+------------+-------------+
|  XLXI_2_tc_clkcnt          |   Local  |    3   |  0.000     |  1.585      |
+----------------------------+----------+--------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 208


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.480
   The MAXIMUM PIN DELAY IS:                               4.898
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   3.019

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
         151         289          72          17          13           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file lcd162.ncd.


PAR done.