📄 lcd162.vhf
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-- VHDL model created from lcd162.sch - Tue Apr 17 11:12:23 2007
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity lcd162 is
port ( clk : in std_logic;
rst : in std_logic;
d : out std_logic_vector (7 downto 0);
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic);
end lcd162;
architecture BEHAVIORAL of lcd162 is
component lcd2
port ( clk : in std_logic;
Reset : in std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_e : out std_logic;
data : out std_logic_vector (7 downto 0));
end component;
begin
XLXI_2 : lcd2
port map (clk=>clk, Reset=>rst, data(7 downto 0)=>d(7 downto 0),
lcd_e=>lcd_e, lcd_rs=>lcd_rs, lcd_rw=>lcd_rw);
end BEHAVIORAL;
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