lcd162.syr

在LCD上显示事先就输入好的字符,可以任意改变的

#      4-bit adder                 : 1
#      7-bit adder                 : 1
# Comparators                      : 2
#      4-bit comparator less       : 1
#      7-bit comparator less       : 1

Cell Usage :
# BELS                             : 205
#      GND                         : 1
#      LUT1                        : 15
#      LUT2                        : 8
#      LUT3                        : 21
#      LUT3_L                      : 4
#      LUT4                        : 54
#      LUT4_D                      : 2
#      LUT4_L                      : 22
#      MUXCY                       : 28
#      MUXF5                       : 14
#      MUXF6                       : 7
#      VCC                         : 1
#      XORCY                       : 28
# FlipFlops/Latches                : 41
#      FDC                         : 15
#      FDC_1                       : 1
#      FDCE                        : 5
#      FDCPE                       : 19
#      FDP                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 12
#      IBUF                        : 1
#      OBUF                        : 3
#      OBUFT                       : 8
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50tq144-5 

 Number of Slices:                      72  out of    768     9%  
 Number of Slice Flip Flops:            41  out of   1536     2%  
 Number of 4 input LUTs:               126  out of   1536     8%  
 Number of bonded IOBs:                 12  out of     96    12%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
XLXI_2_clk_int:Q                   | NONE                   | 19    |
clk                                | BUFGP                  | 19    |
XLXI_2_tc_clkcnt(XLXI_2__n001285:O)| NONE(*)(XLXI_2_clkdiv) | 1     |
XLXI_2_clkdiv:Q                    | NONE                   | 2     |
-----------------------------------+------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 11.268ns (Maximum Frequency: 88.747MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 25.840ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_clk_int:Q'
Delay:               8.171ns (Levels of Logic = 2)
  Source:            XLXI_2_state_9 (FF)
  Destination:       XLXI_2_counter_6 (FF)
  Source Clock:      XLXI_2_clk_int:Q rising
  Destination Clock: XLXI_2_clk_int:Q rising

  Data Path: XLXI_2_state_9 to XLXI_2_counter_6
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              9   1.292   2.120  XLXI_2_state_9 (XLXI_2_state_9)
     LUT4:I0->O           15   0.653   2.700  Ker32661 (N3268)
     LUT4_L:I3->LO         1   0.653   0.000  XLXI_2__n0017<4>1 (XLXI_2__n0017<4>)
     FDC:D                     0.753          XLXI_2_counter_4
    ----------------------------------------
    Total                      8.171ns (3.351ns logic, 4.820ns route)
                                       (41.0% logic, 59.0% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               11.268ns (Levels of Logic = 19)
  Source:            XLXI_2_clkcnt_7 (FF)
  Destination:       XLXI_2_clkcnt_18 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: XLXI_2_clkcnt_7 to XLXI_2_clkcnt_18
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCPE:C->Q            2   1.292   1.340  XLXI_2_clkcnt_7 (XLXI_2_clkcnt_7)
     LUT4:I0->O            2   0.653   1.340  XLXI_2__n001219 (CHOICE49)
     LUT2:I1->O           14   0.653   2.600  XLXI_2__n001220 (CHOICE50)
     LUT4_L:I0->LO         1   0.653   0.000  XLXI_2_clkcnt_inst_lut3_101 (XLXI_2_clkcnt_inst_lut3_10)
     MUXCY:S->O            1   0.784   0.000  XLXI_2_clkcnt_inst_cy_4 (XLXI_2_clkcnt_inst_cy_4)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_5 (XLXI_2_clkcnt_inst_cy_5)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_6 (XLXI_2_clkcnt_inst_cy_6)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_7 (XLXI_2_clkcnt_inst_cy_7)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_8 (XLXI_2_clkcnt_inst_cy_8)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_9 (XLXI_2_clkcnt_inst_cy_9)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_10 (XLXI_2_clkcnt_inst_cy_10)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_11 (XLXI_2_clkcnt_inst_cy_11)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_12 (XLXI_2_clkcnt_inst_cy_12)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_13 (XLXI_2_clkcnt_inst_cy_13)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_14 (XLXI_2_clkcnt_inst_cy_14)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_15 (XLXI_2_clkcnt_inst_cy_15)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_16 (XLXI_2_clkcnt_inst_cy_16)
     MUXCY:CI->O           1   0.050   0.000  XLXI_2_clkcnt_inst_cy_17 (XLXI_2_clkcnt_inst_cy_17)
     MUXCY:CI->O           0   0.050   0.000  XLXI_2_clkcnt_inst_cy_18 (XLXI_2_clkcnt_inst_cy_18)
     XORCY:CI->O           1   0.500   0.000  XLXI_2_clkcnt_inst_sum_18 (XLXI_2_clkcnt_inst_sum_18)
     FDCPE:D                   0.753          XLXI_2_clkcnt_18
    ----------------------------------------
    Total                     11.268ns (5.988ns logic, 5.280ns route)
                                       (53.1% logic, 46.9% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2__n001285:O'
Delay:               4.178ns (Levels of Logic = 1)
  Source:            XLXI_2_clkdiv (FF)
  Destination:       XLXI_2_clkdiv (FF)
  Source Clock:      XLXI_2__n001285:O rising
  Destination Clock: XLXI_2__n001285:O rising

  Data Path: XLXI_2_clkdiv to XLXI_2_clkdiv
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   1.292   1.480  XLXI_2_clkdiv (XLXI_2_clkdiv)
     LUT1:I0->O            1   0.653   0.000  XLXI_2__n00391 (XLXI_2__n0039)
     FDC:D                     0.753          XLXI_2_clkdiv
    ----------------------------------------
    Total                      4.178ns (2.698ns logic, 1.480ns route)
                                       (64.6% logic, 35.4% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'XLXI_2_clkdiv:Q'
Delay:               5.898ns (Levels of Logic = 1)
  Source:            XLXI_2_clk_int (FF)
  Destination:       XLXI_2_clk_int (FF)
  Source Clock:      XLXI_2_clkdiv:Q rising
  Destination Clock: XLXI_2_clkdiv:Q rising

  Data Path: XLXI_2_clk_int to XLXI_2_clk_int
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q             20   1.292   3.200  XLXI_2_clk_int (XLXI_2_clk_int)
     LUT1:I0->O            1   0.653   0.000  XLXI_2__n00401 (XLXI_2__n0040)
     FDC:D                     0.753          XLXI_2_clk_int
    ----------------------------------------
    Total                      5.898ns (2.698ns logic, 3.200ns route)
                                       (45.7% logic, 54.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2_clkdiv:Q'
Offset:              8.189ns (Levels of Logic = 1)
  Source:            XLXI_2_lcd_e (FF)
  Destination:       lcd_e (PAD)
  Source Clock:      XLXI_2_clkdiv:Q falling

  Data Path: XLXI_2_lcd_e to lcd_e
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            2   1.292   1.340  XLXI_2_lcd_e (XLXI_2_lcd_e)
     OBUF:I->O                 5.557          lcd_e_OBUF (lcd_e)
    ----------------------------------------
    Total                      8.189ns (6.849ns logic, 1.340ns route)
                                       (83.6% logic, 16.4% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'XLXI_2_clk_int:Q'
Offset:              25.840ns (Levels of Logic = 8)
  Source:            XLXI_2_state_9 (FF)
  Destination:       d<3> (PAD)
  Source Clock:      XLXI_2_clk_int:Q rising

  Data Path: XLXI_2_state_9 to d<3>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              9   1.292   2.120  XLXI_2_state_9 (XLXI_2_state_9)
     LUT4:I0->O           15   0.653   2.700  Ker32661 (N3268)
     LUT2:I0->O           33   0.653   3.850  XLXI_2_char_addr<0>1 (XLXI_2_char_addr<0>)
     LUT4:I0->O            1   0.653   1.150  XLXI_2_aa_Mrom_data_inst_mux_f6_5_SW0 (N3911)
     LUT3:I2->O            1   0.653   1.150  XLXI_2_aa_Mrom_data_inst_mux_f6_5 (XLXI_2_aa_Mrom_data__net19)
     LUT3:I2->O            1   0.653   1.150  XLXI_2_aa_Mrom_data_inst_lut3_21 (XLXI_2_data_in<2>)
     LUT3:I2->O            1   0.653   1.150  XLXI_2__n0022<2>_SW0 (N3454)
     LUT4:I3->O            1   0.653   1.150  XLXI_2__n0022<2> (d_2_OBUFT)
     OBUFT:I->O                5.557          d_2_OBUFT (d<2>)
    ----------------------------------------
    Total                     25.840ns (11.420ns logic, 14.420ns route)
                                       (44.2% logic, 55.8% route)

=========================================================================
CPU : 5.02 / 7.06 s | Elapsed : 5.00 / 7.00 s
 
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Total memory usage is 58476 kilobytes