lcd162.syr

在LCD上显示事先就输入好的字符,可以任意改变的

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: lcd162.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : lcd162.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : lcd162
Output Format                      : NGC
Target Device                      : xc2s50-5-tq144

---- Source Options
Top Module Name                    : lcd162
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : lcd162.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file E:/lcd1621/lcd1621/lcd2.vhdl in Library work.
Architecture behavioral of Entity char2 is up to date.
Architecture behavioral of Entity lcd2 is up to date.
Compiling vhdl file E:/lcd1621/lcd1621/lcd162.vhf in Library work.
Entity <lcd162> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <lcd162> (Architecture <behavioral>).
INFO:Xst:1739 - HDL ADVISOR - E:/lcd1621/lcd1621/lcd162.vhf line 222: declaration of a buffer port will make it difficult for you to validate this design by simulation. It is preferable to declare it as output.
Entity <lcd162> analyzed. Unit <lcd162> generated.

Analyzing Entity <lcd2> (Architecture <behavioral>).
Entity <lcd2> analyzed. Unit <lcd2> generated.

Analyzing Entity <char2> (Architecture <behavioral>).
Entity <char2> analyzed. Unit <char2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <char2>.
    Related source file is E:/lcd1621/lcd1621/lcd2.vhdl.
    Found 128x8-bit ROM for signal <data>.
    Summary:
	inferred   1 ROM(s).
Unit <char2> synthesized.


Synthesizing Unit <lcd2>.
    Related source file is E:/lcd1621/lcd1621/lcd2.vhdl.
    Using one-hot encoding for signal <state>.
    Found 1-bit register for signal <lcd_e>.
    Found 8-bit tristate buffer for signal <data>.
    Found 4-bit comparator less for signal <$n0007> created at line 344.
    Found 7-bit comparator less for signal <$n0008> created at line 362.
    Found 7-bit adder for signal <$n0027> created at line 363.
    Found 4-bit adder for signal <$n0030> created at line 345.
    Found 1-bit register for signal <clk_int>.
    Found 19-bit up counter for signal <clkcnt>.
    Found 1-bit register for signal <clkdiv>.
    Found 7-bit register for signal <counter>.
    Found 4-bit register for signal <div_counter>.
    Found 1-bit register for signal <flag>.
    Found 11-bit register for signal <state>.
    Summary:
	inferred   1 Counter(s).
	inferred  15 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   2 Comparator(s).
	inferred   8 Tristate(s).
Unit <lcd2> synthesized.


Synthesizing Unit <lcd162>.
    Related source file is E:/lcd1621/lcd1621/lcd162.vhf.
Unit <lcd162> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
 128x8-bit ROM                     : 1
# Adders/Subtractors               : 2
 4-bit adder                       : 1
 7-bit adder                       : 1
# Counters                         : 1
 19-bit up counter                 : 1
# Registers                        : 7
 4-bit register                    : 1
 1-bit register                    : 4
 7-bit register                    : 1
 11-bit register                   : 1
# Comparators                      : 2
 7-bit comparator less             : 1
 4-bit comparator less             : 1
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <XLXI_2_state_8> (without init value) is constant in block <lcd162>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_state_10> (without init value) is constant in block <lcd162>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_state_2> (without init value) is constant in block <lcd162>.
WARNING:Xst:1710 - FF/Latch  <XLXI_2_state_7> (without init value) is constant in block <lcd162>.

Optimizing unit <lcd162> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block lcd162, actual ratio is 9.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : lcd162.ngr
Top Level Output File Name         : lcd162
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 13

Macro Statistics :
# ROMs                             : 1
#      128x8-bit ROM               : 1
# Registers                        : 17
#      1-bit register              : 15
#      4-bit register              : 1
#      7-bit register              : 1
# Counters                         : 1
#      19-bit up counter           : 1
# Tristates                        : 1
#      8-bit tristate buffer       : 1
# Adders/Subtractors               : 2