sync_gen_50m.v

本示例演示了VGA的控制方法

////////////////////////////////////////////////////////////////////////////////
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//                                                                            //
////////////////////////////////////////////////////////////////////////////////
// 	   Copyright (C) 2003-2006 VibesIC, Inc.   All rights reserved.           //
//----------------------------------------------------------------------------//
// This source code is provided by VibesIC, and be verified on VibesIC FPGA   //
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////////////////////////////////////////////////////////////////////////////////
//  Company:       www.richic.com                                             //
//  Company bbs:   www.edacn.net                                              //
//  Engineer:      mail007 (Gavin.xue)                                        //
//                                                                            //
//  Target Device: XC3S400-PQ208                                              //
//  Tool versions: Simulation:    ModelSim SE 6.2a                            //
//                 Synthesis:     XST(ise8.1...sp3)                           //
//                 Place&Routing: ISE8.1...sp3                                //
//                 Others tools:  UltraEdit-32 12.10a                         //
//  Create Date:   2005-9-6 10:59                                             //
//  Description:                                                              //
//                                                                            //
//  LOG:                                                                      //
//       1. Revision 1.0 (Initial version)  2005-9-6 10:59    mail007         //
//                                                                            //
//       2. Revision 1.1  2006-12-27 17:12   alex_yang                        //
//          Updata ISE version from v6.3 to v8.1                              //
//          Modify for VX-SP306                                               //

////////////////////////////////////////////////////////////////////////////////

module sync_gen_50m(
                    clk,
                    rst_n,
                    hsync,
                    vsync,
                    valid,
                    x_cnt,
                    y_cnt
                    );

input           clk;
input           rst_n;
output          hsync;
output          vsync;
output          valid;
output  [9:0]   x_cnt;
output  [9:0]   y_cnt;

reg             hsync;
reg             vsync;
reg             valid;
reg     [9:0]   x_cnt;
reg     [9:0]   y_cnt;

  // ---------------------------------------------------------------------------
  // 两个Always 中可以使用相同的判断条件
  // ---------------------------------------------------------------------------
  always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
      x_cnt <= 10'd0;
    else if ( x_cnt == 10'd1000 )
      x_cnt <= 10'd0;
    else
      x_cnt <= x_cnt + 1'b1;
          
  always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
      y_cnt <= 10'd0;
    else if ( y_cnt == 10'd665 )
      y_cnt <= 10'd0;    
    else if ( x_cnt == 10'd1000 )
      y_cnt <= y_cnt + 1'b1;    

  // ---------------------------------------------------------------------------
  // hsync <= x_cnt <= 10'd50；中第一个“<=”为赋值语句，第二个“<=”为比较语句
  // 本代码的操作为：比较后再赋值。
  // ---------------------------------------------------------------------------        
  always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
      begin
        hsync <= 1'b0;
        vsync <= 1'b0;
      end
    else
      begin
        hsync <= x_cnt <= 10'd50;  //产生hsync信号
        vsync <= y_cnt <= 10'd6;   //产生vsync信号
      end    
  
  always @ ( posedge clk or negedge rst_n )                     
    if ( !rst_n )
      valid <= 1'b0;
    else
      valid <= ( ( x_cnt > 10'd180 ) && ( x_cnt < 10'd980) &&
                 ( y_cnt > 10'd35)   && ( y_cnt < 10'd635) ); 
                      
endmodule