watch.rpt

此为秒表程序

Warning: Line 104: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig2" in a Process Statement -- only the last assignment will take effect
Warning: Line 102: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig2" in a Process Statement -- only the last assignment will take effect
Warning: Line 100: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig2" in a Process Statement -- only the last assignment will take effect
Warning: Line 116: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 114: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 112: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 110: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 108: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 106: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 104: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 102: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 100: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig1" in a Process Statement -- only the last assignment will take effect
Warning: Line 116: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 114: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 112: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 110: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 108: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 106: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 104: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 102: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect
Warning: Line 100: File f:\watch\watch.vhd: Found multiple assignments to the same signal or signal bit "segsig0" in a Process Statement -- only the last assignment will take effect


Project Information                                         f:\watch\watch.rpt

** FILE HIERARCHY **



|lpm_add_sub:307|
|lpm_add_sub:307|addcore:adder|
|lpm_add_sub:307|altshift:result_ext_latency_ffs|
|lpm_add_sub:307|altshift:carry_ext_latency_ffs|
|lpm_add_sub:307|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:366|
|lpm_add_sub:366|addcore:adder|
|lpm_add_sub:366|altshift:result_ext_latency_ffs|
|lpm_add_sub:366|altshift:carry_ext_latency_ffs|
|lpm_add_sub:366|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:425|
|lpm_add_sub:425|addcore:adder|
|lpm_add_sub:425|altshift:result_ext_latency_ffs|
|lpm_add_sub:425|altshift:carry_ext_latency_ffs|
|lpm_add_sub:425|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:484|
|lpm_add_sub:484|addcore:adder|
|lpm_add_sub:484|altshift:result_ext_latency_ffs|
|lpm_add_sub:484|altshift:carry_ext_latency_ffs|
|lpm_add_sub:484|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:543|
|lpm_add_sub:543|addcore:adder|
|lpm_add_sub:543|altshift:result_ext_latency_ffs|
|lpm_add_sub:543|altshift:carry_ext_latency_ffs|
|lpm_add_sub:543|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:602|
|lpm_add_sub:602|addcore:adder|
|lpm_add_sub:602|altshift:result_ext_latency_ffs|
|lpm_add_sub:602|altshift:carry_ext_latency_ffs|
|lpm_add_sub:602|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:2651|
|lpm_add_sub:2651|addcore:adder|
|lpm_add_sub:2651|altshift:result_ext_latency_ffs|
|lpm_add_sub:2651|altshift:carry_ext_latency_ffs|
|lpm_add_sub:2651|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                                f:\watch\watch.rpt
watch

***** Logic for device 'watch' compiled without errors.




Device: EPF10K10LC84-3

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                         ^     
                                                                         C     
                R  R  R  R  R  R  R                 R     R  R  R  R     O     
                E  E  E  E  E  E  E                 E     E  E  E  E     N     
                S  S  S  S  S  S  S  V           G  S  G  S  S  S  S     F     
                E  E  E  E  E  E  E  C     r     N  E  N  E  E  E  E     _  ^  
                R  R  R  R  R  R  R  C  s  e     D  R  D  R  R  R  R  #  D  n  
                V  V  V  V  V  V  V  I  e  s  c  I  V  I  V  V  V  V  T  O  C  
                E  E  E  E  E  E  E  N  l  e  p  N  E  N  E  E  E  E  C  N  E  
                D  D  D  D  D  D  D  T  5  t  2  T  D  T  D  D  D  D  K  E  O  
              -----------------------------------------------------------------_ 
            /  11 10  9  8  7  6  5  4  3  2  1 84 83 82 81 80 79 78 77 76 75   | 
    ^DATA0 | 12                                                              74 | #TDO 
     ^DCLK | 13                                                              73 | RESERVED 
      ^nCE | 14                                                              72 | RESERVED 
      #TDI | 15                                                              71 | RESERVED 
  RESERVED | 16                                                              70 | RESERVED 
  RESERVED | 17                                                              69 | RESERVED 
  RESERVED | 18                                                              68 | GNDINT 
  RESERVED | 19                                                              67 | RESERVED 
    VCCINT | 20                                                              66 | RESERVED 
      sel2 | 21                                                              65 | RESERVED 
      sel4 | 22                        EPF10K10LC84-3                        64 | RESERVED 
      sel3 | 23                                                              63 | VCCINT 
      sel1 | 24                                                              62 | seg7 
      sel6 | 25                                                              61 | seg5 
    GNDINT | 26                                                              60 | seg4 
      seg2 | 27                                                              59 | seg3 
      seg1 | 28                                                              58 | seg6 
  RESERVED | 29                                                              57 | #TMS 
      seg0 | 30                                                              56 | #TRST 
    ^MSEL0 | 31                                                              55 | ^nSTATUS 
    ^MSEL1 | 32                                                              54 | RESERVED 
           |_  33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53  _| 
             ------------------------------------------------------------------ 
                V  ^  R  R  R  R  R  V  G  b  c  G  V  G  R  R  R  R  R  R  R  
                C  n  E  E  E  E  E  C  N  e  p  N  C  N  E  E  E  E  E  E  E  
                C  C  S  S  S  S  S  C  D  g  3  D  C  D  S  S  S  S  S  S  S  
                I  O  E  E  E  E  E  I  I  i     I  I  I  E  E  E  E  E  E  E  
                N  N  R  R  R  R  R  N  N  n     N  N  N  R  R  R  R  R  R  R  
                T  F  V  V  V  V  V  T  T  s     T  T  T  V  V  V  V  V  V  V  
                   I  E  E  E  E  E        t              E  E  E  E  E  E  E  
                   G  D  D  D  D  D        o              D  D  D  D  D  D  D  
                                           p                                   
                                                                               


N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:                                f:\watch\watch.rpt
watch

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
B4       7/ 8( 87%)   0/ 8(  0%)   7/ 8( 87%)    1/2    0/2       2/22(  9%)   
B6       1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    1/2    1/2       1/22(  4%)   
B11      8/ 8(100%)   1/ 8( 12%)   7/ 8( 87%)    1/2    0/2       1/22(  4%)   
B12      1/ 8( 12%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       2/22(  9%)   
B13      8/ 8(100%)   1/ 8( 12%)   3/ 8( 37%)    2/2    1/2      15/22( 68%)   
B14      8/ 8(100%)   0/ 8(  0%)   7/ 8( 87%)    1/2    1/2       8/22( 36%)   
B15      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    1/2       4/22( 18%)   
B16      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    1/2       4/22( 18%)   
B17      8/ 8(100%)   0/ 8(  0%)   6/ 8( 75%)    1/2    1/2       4/22( 18%)   
B18      2/ 8( 25%)   0/ 8(  0%)   2/ 8( 25%)    1/2    1/2       3/22( 13%)   
B19      6/ 8( 75%)   1/ 8( 12%)   0/ 8(  0%)    1/2    0/2      12/22( 54%)   
B20      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    1/2       5/22( 22%)   
B21      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    1/2    1/2       4/22( 18%)   
B22      6/ 8( 75%)   1/ 8( 12%)   0/ 8(  0%)    1/2    0/2      12/22( 54%)   
B23      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    1/2    1/2       3/22( 13%)   
B24      7/ 8( 87%)   1/ 8( 12%)   1/ 8( 12%)    2/2    1/2      14/22( 63%)   
C15      8/ 8(100%)   0/ 8(  0%)   5/ 8( 62%)    0/2    0/2      10/22( 45%)   
C21      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2      10/22( 45%)   
C23      8/ 8(100%)   0/ 8(  0%)   4/ 8( 50%)    0/2    0/2       8/22( 36%)