sd.v

基于FPGA的SD控制器实现.目前实现读操作功能,可作参考.

//Written by Vladimir Boykov
//Last modification August, 2005

module sd (
            // inputs:
             address,
             base_clock,
             chipselect,
             clk,
             read,
             reset,
             waitrequest,
             write,
             writedata,

            // outputs:
             byteenable,
             clk_to_SD,
             cmd_SD,
             data_SD,
             irq,
             maddress,
             mwrite,
             mwritedata,
             readdata
          );

  output  [  3: 0] byteenable;
  output           clk_to_SD;
  inout            cmd_SD;
  inout   [  3: 0] data_SD;
  output           irq;
  output  [ 31: 0] maddress;
  output           mwrite;
  output  [ 31: 0] mwritedata;
  output  [ 31: 0] readdata;
  input   [  2: 0] address;
  input            base_clock;
  input            chipselect;
  input            clk;
  input            read;
  input            reset;
  input            waitrequest;
  input            write;
  input   [ 31: 0] writedata;

  wire    [  3: 0] byteenable;
  wire             clk_to_SD;
  wire             cmd_SD;
  wire    [  3: 0] data_SD;
  wire             irq;
  wire    [ 31: 0] maddress;
  wire             mwrite;
  wire    [ 31: 0] mwritedata;
  wire    [ 31: 0] readdata;
  sd_host the_sd_host
    (
      .address     (address),
      .base_clock  (base_clock),
      .byteenable  (byteenable),
      .chipselect  (chipselect),
      .clk         (clk),
      .clk_to_SD   (clk_to_SD),
      .cmd_SD      (cmd_SD),
      .data_SD     (data_SD),
      .irq         (irq),
      .maddress    (maddress),
      .mwrite      (mwrite),
      .mwritedata  (mwritedata),
      .read        (read),
      .readdata    (readdata),
      .reset       (reset),
      .waitrequest (waitrequest),
      .write       (write),
      .writedata   (writedata)
    );



endmodule