readme.txt

来自「基于FPGA的SD控制器实现.目前实现读操作功能,可作参考.」· 文本 代码 · 共 10 行

Written by Vladimir Boykov ([e-mail]),
Verilog, last modification August, 2005.
Just for free use not for selling.

SD card controller can just read data using 1 bit SD mode.
I have written this core for NIOS2 CPU, Cyclone, but I think it can works
with other FPGA or CPLD. Better case for this core is SD clock = 20 MHz and
CPU clock = 100 MHz (or in the ratio 1:5). If you have a wish you can achieve this core.
Good luck!!!