class.ptf

基于FPGA的SD控制器实现.目前实现读操作功能,可作参考.

CLASS user_logic_Camelot_SD_Controller
{
   ASSOCIATED_FILES 
   {
      Add_Program = "";
      Edit_Program = "";
      Generator_Program = "mk_user_logic_Camelot_SD_Controller.pl";
   }
   MODULE_DEFAULTS 
   {
      class = "user_logic_Camelot_SD_Controller";
      class_version = "2.0";
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Date_Modified = "--unknown--";
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
      }
      PORT_WIRING 
      {
            PORT clk_to_SD
            {
               width = "1";
               direction = "output";
               type = "export";
            }
            PORT cmd_SD
            {
               width = "1";
               direction = "inout";
               type = "export";
            }
            PORT data_SD
            {
               width = "4";
               direction = "inout";
               type = "export";
            }
            PORT base_clock
            {
               width = "1";
               direction = "input";
               type = "export";
            }
      }
      MASTER sd_avalon_master
      {
            SYSTEM_BUILDER_INFO
	    {
	  	Bus_Type = "avalon";
	  	Address_Width = "32";
		Max_Address_Width = "32";
		Data_Width = "32";
		Is_Enabled = "1";
     	    }
            PORT_WIRING
	    {  
              PORT clk
              {
               width = "1";
               direction = "input";
               type = "clk";
              }
              PORT reset
              {
               width = "1";
               direction = "input";
               type = "reset";
              }
              PORT maddress
              {
               width = "32";
               direction = "output";
               type = "address";
              }
              PORT byteenable
              {
               width = "4";
               direction = "output";
               type = "byteenable";
              }
              PORT mwrite
              {
               width = "1";
               direction = "output";
               type = "write";
              }
              PORT mwritedata
              {
               width = "32";
               direction = "output";
               type = "writedata";
              }
              PORT waitrequest
              {
               width = "1";
               direction = "input";
               type = "waitrequest";
              }
            }
      }
      SLAVE sd_avalon_slave
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "native";
            Address_Width = "3";
            Data_Width = "32";
            Has_IRQ = "1";
            Has_Base_Address = "1";
            Read_Wait_States = "0";
            Write_Wait_States = "0";
            Setup_Time = "0";
            Hold_Time = "0";
            Is_Memory_Device = "0";
            Uses_Tri_State_Data_Bus = "0";
            Is_Enabled = "1";
         }
         PORT_WIRING 
         {
            PORT chipselect
            {
               width = "1";
               direction = "input";
               type = "chipselect";
            }
            PORT address
            {
               width = "3";
               direction = "input";
               type = "address";
            }
            PORT read
            {
               width = "1";
               direction = "input";
               type = "read";
            }
            PORT readdata
            {
               width = "32";
               direction = "output";
               type = "readdata";
            }
            PORT write
            {
               width = "1";
               direction = "input";
               type = "write";
            }
            PORT writedata
            {
               width = "32";
               direction = "input";
               type = "writedata";
            }
            PORT irq
            {
               width = "1";
               direction = "output";
               type = "irq";
            }
         }
      }
   }
   USER_INTERFACE 
   {
      USER_LABELS 
      {
         name = "Camelot_SD_Controller";
         technology = "Camelot";
      }
   }
   DEFAULT_GENERATOR 
   {
      top_module_name = "sd_host";
      black_box = "0";
      vhdl_synthesis_files = "";
      verilog_synthesis_files = "crc_unit_7.v,fifo_buffer.v,sd_controller.v,sd_host.v";
      black_box_files = "";
   }
}