sd_host.v

基于FPGA的SD控制器实现.目前实现读操作功能,可作参考.

//Written by Vladimir Boykov
//Last modification August, 2005

module sd_host (clk, base_clock, reset, chipselect, address, 
                maddress, byteenable, mwritedata, mwrite, waitrequest,
                read, readdata, write, writedata, irq,
                clk_to_SD, cmd_SD, data_SD);

//Avalon Master Interface               
output [31:0] maddress;
output [31:0] mwritedata;
output mwrite;
output [3:0] byteenable;
input waitrequest;

                
//Avalon Slave Interface
input clk;                 //System clock
input base_clock;          //Input 25 MHz
input reset;               //Global reset
input chipselect;          //ChipSelect
input [2:0] address;       //Address for access to internal registers, fifo
input read;                //Read request signal
output [31:0] readdata;    //Data line for read transfer from SD
input write;               //Write request signal
input [31:0] writedata;    //Data line for write transfer to SD
output irq;

//SD Host Interface
output clk_to_SD;          //Clock to SD Card
inout cmd_SD;              //Command/Response to/from SD Card
inout [3:0] data_SD;       //Data line to/from SD Card

//Internal Wires
wire internal_register_data; //Addres > 5'b00001
wire RAMaddress_req, IRQ_disable_req;

wire sd_controller_clock;    //Clock to SD controller

wire aclear_rb;              //Clear read buffer

wire write_to_buf;           //Write from read_buffer
wire [31:0]  from_sd_controller_data; //Output from SD controller
wire [31:0] manreg;          //Internal register of SD controller

//Address selector
assign  RAMaddress_req =  ((address==3'b000) && chipselect && write)? 1 : 0;
assign  IRQ_disable_req =  ((address==3'b001) && chipselect && write)? 1 : 0;

assign internal_register_data = ((address != 3'b000) && (address != 3'b001) && chipselect)? 1 : 0;
assign readdata = (internal_register_data && read)? manreg : 32'bz;

assign clk_to_SD = ~base_clock;
assign sd_controller_clock = base_clock;

//Master's variables
reg [31:0] temp, startRAMaddress;
reg [3:0] com;
reg [7:0] num;
reg wr;
reg irq_enable;

assign maddress = (startRAMaddress + {22'd0, num, 2'b00});
assign byteenable = 4'b1111;
assign mwrite = wr;
assign mwritedata = temp;
assign irq = irq_enable;

always @ (posedge clk or posedge reset) begin
   if (reset) begin
      irq_enable <= 1'b0;
   end else begin
      if (num==8'd128) irq_enable <= 1'b1;
      else if(IRQ_disable_req) irq_enable <= 1'b0;
   end
end

always @ (posedge clk or posedge reset) begin
   if (reset) begin
      startRAMaddress <= 32'd0;
   end else begin
      if (RAMaddress_req) startRAMaddress <= writedata;
   end
end

always @ (posedge clk or posedge reset or posedge aclear_rb) begin
   if (reset || aclear_rb) begin
      temp <= 32'd0;
      num <= 8'd0;
      wr <= 1'b0;
      com <= 3'd7;
   end else begin
      case (com)
         3'd0: begin
            wr <= 1'b1;
            com <= 3'd1;
         end
         3'd1: begin
            if (!waitrequest) begin
               wr <= 1'b0;
               num <= num + 8'd1;
               com <= 3'd2;
            end
         end
         3'd2: begin
            com <= 3'd3;
         end
         3'd3: begin
            if (num == 8'd128) num <= 8'd0;
            com <= 3'd4;
         end
         3'd4: begin
            com <= 3'd5;
         end
         3'd5: begin
            com <= 3'd6;
         end
         3'd6: begin
            com <= 3'd7;
         end
         3'd7: begin   
            if (write_to_buf) begin
               temp <= from_sd_controller_data;
               com <= 3'd0;
            end
         end
      endcase
   end
end
                                              
//SD card Controller
sd_controller SD (
                  .sys_clk(clk), 
                  .sd_clk(sd_controller_clock),
                  .reset(reset),
                  .cs(chipselect),
                  .sd_cmd(cmd_SD),
                  .address(address),
                  .sd_data(data_SD),
                  .data_input(writedata),
                  .data_output(from_sd_controller_data),
                  .write_to_buffer(write_to_buf), 
                  .write(write),
                  .read(read),
                  .int_reg(manreg),
                  .clear (aclear_rb)
                 );                         
    
endmodule