fq_divider.vhd

分频器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fq_divider IS
generic(n:integer:=1667);
PORT(
CLK,reset: IN STD_LOGIC;
CLK_OUT:buffer STD_LOGIC
);
END;
ARCHITECTURE A OF fq_divider IS
SIGNAL CNT1,CNT2:integer:=0;
SIGNAL OUTTEMP:STD_LOGIC;
BEGIN
P1:PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
   IF CNT1=n-1 THEN
      CNT1<=0;
   ELSE
      CNT1<=CNT1+1;
   END IF;
END IF;
END PROCESS P1;
P2:PROCESS(CLK,reset)
BEGIN
 IF CLK'EVENT AND CLK='0' THEN
   IF CNT2=n-1 THEN
      CNT2<=0;
   ELSE 
      CNT2<=CNT2+1;
   END IF;
END IF;
END PROCESS P2;
P3:PROCESS(CNT1,CNT2)
BEGIN
 if reset='1'then
   OUTTEMP<='0';
 elsif ((n mod 2)=1) then
   IF CNT1=1 THEN
      IF CNT2=0 THEN
         OUTTEMP<='1';
      ELSE 
         OUTTEMP<='0';
      END IF;   
    ELSIF CNT1=(n+1)/2 THEN
          IF CNT2=(n+1)/2 THEN
             OUTTEMP<='1';
          ELSE OUTTEMP<='0';
          END IF;
    ELSE 
          OUTTEMP<='0';
    END IF;
   else
    if cnt1=1 then
       outtemp<='1';
    elsif (cnt1=(n/2+1)) then
       outtemp<='1';
    else
       outtemp<='0';
  end if;
 end if;
END PROCESS P3;
clk_out<=outtemp;
END A;