lian_translate.v

在ise下设计的蝶形变换程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: I.24
//  \   \         Application: netgen
//  /   /         Filename: lian_translate.v
// /___/   /\     Timestamp: Tue Nov 21 22:54:52 2006
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -intstyle ise -w -dir netgen/translate -ofmt verilog -sim lian.ngd lian_translate.v 
// Device	: 3s400pq208-4
// Input file	: lian.ngd
// Output file	: D:\xilinx\lianxi\diexingbianhuan\netgen\translate\lian_translate.v
// # of Modules	: 1
// Design Name	: lian
// Xilinx        : D:\xilinx
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module lian (
  clk, cps_in, Are_in, Aim_in, Bre_in, Bim_in, cms_in, c_in, Ere_out, Dre_out, Eim_out, Dim_out
);
  input clk;
  input [8 : 0] cps_in;
  input [7 : 0] Are_in;
  input [7 : 0] Aim_in;
  input [7 : 0] Bre_in;
  input [7 : 0] Bim_in;
  input [8 : 0] cms_in;
  input [7 : 0] c_in;
  output [7 : 0] Ere_out;
  output [7 : 0] Dre_out;
  output [7 : 0] Eim_out;
  output [7 : 0] Dim_out;
  wire clk_BUFGP;
  wire cps_in_8_IBUF_1;
  wire cps_in_7_IBUF_2;
  wire cps_in_6_IBUF_3;
  wire cps_in_5_IBUF_4;
  wire cps_in_4_IBUF_5;
  wire cps_in_3_IBUF_6;
  wire cps_in_2_IBUF_7;
  wire cps_in_1_IBUF_8;
  wire cps_in_0_IBUF_9;
  wire Are_in_7_IBUF_10;
  wire Are_in_6_IBUF_11;
  wire Are_in_5_IBUF_12;
  wire Are_in_4_IBUF_13;
  wire Are_in_3_IBUF_14;
  wire Are_in_2_IBUF_15;
  wire Are_in_1_IBUF_16;
  wire Are_in_0_IBUF_17;
  wire Aim_in_7_IBUF_18;
  wire Aim_in_6_IBUF_19;
  wire Aim_in_5_IBUF_20;
  wire Aim_in_4_IBUF_21;
  wire Aim_in_3_IBUF_22;
  wire Aim_in_2_IBUF_23;
  wire Aim_in_1_IBUF_24;
  wire Aim_in_0_IBUF_25;
  wire Bre_in_7_IBUF_26;
  wire Bre_in_6_IBUF_27;
  wire Bre_in_5_IBUF_28;
  wire Bre_in_4_IBUF_29;
  wire Bre_in_3_IBUF_30;
  wire Bre_in_2_IBUF_31;
  wire Bre_in_1_IBUF_32;
  wire Bre_in_0_IBUF_33;
  wire Bim_in_7_IBUF_34;
  wire Bim_in_6_IBUF_35;
  wire Bim_in_5_IBUF_36;
  wire Bim_in_4_IBUF_37;
  wire Bim_in_3_IBUF_38;
  wire Bim_in_2_IBUF_39;
  wire Bim_in_1_IBUF_40;
  wire Bim_in_0_IBUF_41;
  wire cms_in_8_IBUF_42;
  wire cms_in_7_IBUF_43;
  wire cms_in_6_IBUF_44;
  wire cms_in_5_IBUF_45;
  wire cms_in_4_IBUF_46;
  wire cms_in_3_IBUF_47;
  wire cms_in_2_IBUF_48;
  wire cms_in_1_IBUF_49;
  wire cms_in_0_IBUF_50;
  wire c_in_7_IBUF_51;
  wire c_in_6_IBUF_52;
  wire c_in_5_IBUF_53;
  wire c_in_4_IBUF_54;
  wire c_in_3_IBUF_55;
  wire c_in_2_IBUF_56;
  wire c_in_1_IBUF_57;
  wire c_in_0_IBUF_58;
  wire N0;
  wire N1;
  wire \XLXI_1/N7 ;
  wire \XLXI_1/ccmul_cyo ;
  wire \XLXI_1/N8 ;
  wire \XLXI_1/ccmul_cyo1 ;
  wire \XLXI_1/N9 ;
  wire \XLXI_1/ccmul_cyo2 ;
  wire \XLXI_1/N10 ;
  wire \XLXI_1/ccmul_cyo3 ;
  wire \XLXI_1/N11 ;
  wire \XLXI_1/ccmul_cyo4 ;
  wire \XLXI_1/N12 ;
  wire \XLXI_1/ccmul_cyo5 ;
  wire \XLXI_1/N13 ;
  wire \XLXI_1/ccmul_cyo6 ;
  wire \XLXI_1/N14 ;
  wire \XLXI_1/ccmul_cyo7 ;
  wire \XLXI_1/N15 ;
  wire \XLXI_1/ccmul_i<8>_cyo ;
  wire \XLXI_1/N16 ;
  wire \XLXI_1/ccmul_i<9>_cyo ;
  wire \XLXI_1/N17 ;
  wire \XLXI_1/ccmul_i<10>_cyo ;
  wire \XLXI_1/N18 ;
  wire \XLXI_1/ccmul_i<11>_cyo ;
  wire \XLXI_1/N19 ;
  wire \XLXI_1/ccmul_i<12>_cyo ;
  wire \XLXI_1/N20 ;
  wire \XLXI_1/ccmul_i<13>_cyo ;
  wire \XLXI_1/N21 ;
  wire \XLXI_1/ccmul_i<14>_cyo ;
  wire \XLXI_1/N22 ;
  wire \XLXI_1/N24 ;
  wire \XLXI_1/ccmul_xmy<0>_cyo ;
  wire \XLXI_1/N25 ;
  wire \XLXI_1/ccmul_xmy<1>_cyo ;
  wire \XLXI_1/N26 ;
  wire \XLXI_1/ccmul_xmy<2>_cyo ;
  wire \XLXI_1/N27 ;
  wire \XLXI_1/ccmul_xmy<3>_cyo ;
  wire \XLXI_1/N28 ;
  wire \XLXI_1/ccmul_xmy<4>_cyo ;
  wire \XLXI_1/N29 ;
  wire \XLXI_1/ccmul_xmy<5>_cyo ;
  wire \XLXI_1/N30 ;
  wire \XLXI_1/ccmul_xmy<6>_cyo ;
  wire \XLXI_1/N31 ;
  wire \XLXI_1/ccmul_xmy<7>_cyo ;
  wire \XLXI_1/N33 ;
  wire \XLXI_1/ccmul_cyo9 ;
  wire \XLXI_1/N34 ;
  wire \XLXI_1/ccmul_cyo10 ;
  wire \XLXI_1/N35 ;
  wire \XLXI_1/ccmul_cyo11 ;
  wire \XLXI_1/N36 ;
  wire \XLXI_1/ccmul_cyo12 ;
  wire \XLXI_1/N37 ;
  wire \XLXI_1/ccmul_cyo13 ;
  wire \XLXI_1/N38 ;
  wire \XLXI_1/ccmul_cyo14 ;
  wire \XLXI_1/N39 ;
  wire \XLXI_1/ccmul_cyo15 ;
  wire \XLXI_1/N40 ;
  wire \XLXI_1/ccmul_cyo16 ;
  wire \XLXI_1/N41 ;
  wire \XLXI_1/ccmul_r<8>_cyo ;
  wire \XLXI_1/N42 ;
  wire \XLXI_1/ccmul_r<9>_cyo ;
  wire \XLXI_1/N43 ;
  wire \XLXI_1/ccmul_r<10>_cyo ;
  wire \XLXI_1/N44 ;
  wire \XLXI_1/ccmul_r<11>_cyo ;
  wire \XLXI_1/N45 ;
  wire \XLXI_1/ccmul_r<12>_cyo ;
  wire \XLXI_1/N46 ;
  wire \XLXI_1/ccmul_r<13>_cyo ;
  wire \XLXI_1/N47 ;
  wire \XLXI_1/ccmul_r<14>_cyo ;
  wire \XLXI_1/N48 ;
  wire N01;
  wire \XLXI_2/N37 ;
  wire \XLXI_2/N35 ;
  wire \XLXI_2/N32 ;
  wire \XLXI_2/N30 ;
  wire \XLXI_2/N27 ;
  wire \XLXI_2/N25 ;
  wire \XLXI_2/N22 ;
  wire \XLXI_2/N20 ;
  wire \XLXI_2/N17 ;
  wire \XLXI_2/N15 ;
  wire \XLXI_2/N12 ;
  wire \XLXI_2/N10 ;
  wire \XLXI_2/N7 ;
  wire \XLXI_2/N5 ;
  wire \XLXI_2/N2 ;
  wire \XLXI_2/N0 ;
  wire \XLXI_3/N37 ;
  wire \XLXI_3/N35 ;
  wire \XLXI_3/N32 ;
  wire \XLXI_3/N30 ;
  wire \XLXI_3/N27 ;
  wire \XLXI_3/N25 ;
  wire \XLXI_3/N22 ;
  wire \XLXI_3/N20 ;
  wire \XLXI_3/N17 ;
  wire \XLXI_3/N15 ;
  wire \XLXI_3/N12 ;
  wire \XLXI_3/N10 ;
  wire \XLXI_3/N7 ;
  wire \XLXI_3/N5 ;
  wire \XLXI_3/N2 ;
  wire \XLXI_3/N0 ;
  wire \XLXI_4/N37 ;
  wire \XLXI_4/N35 ;
  wire \XLXI_4/N32 ;
  wire \XLXI_4/N30 ;
  wire \XLXI_4/N27 ;
  wire \XLXI_4/N25 ;
  wire \XLXI_4/N22 ;
  wire \XLXI_4/N20 ;
  wire \XLXI_4/N17 ;
  wire \XLXI_4/N15 ;
  wire \XLXI_4/N12 ;
  wire \XLXI_4/N10 ;
  wire \XLXI_4/N7 ;
  wire \XLXI_4/N5 ;
  wire \XLXI_4/N2 ;
  wire \XLXI_4/N0 ;
  wire \XLXI_5/N37 ;
  wire \XLXI_5/N35 ;
  wire \XLXI_5/N32 ;
  wire \XLXI_5/N30 ;
  wire \XLXI_5/N27 ;
  wire \XLXI_5/N25 ;
  wire \XLXI_5/N22 ;
  wire \XLXI_5/N20 ;
  wire \XLXI_5/N17 ;
  wire \XLXI_5/N15 ;
  wire \XLXI_5/N12 ;
  wire \XLXI_5/N10 ;
  wire \XLXI_5/N7 ;
  wire \XLXI_5/N5 ;
  wire \XLXI_5/N2 ;
  wire \XLXI_5/N0 ;
  wire \clk_BUFGP/IBUFG_59 ;
  wire VCC;
  wire GND;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[35]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[34]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[33]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[32]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[31]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[30]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[29]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[28]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[27]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[26]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[25]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[24]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[23]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[22]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[21]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[20]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[19]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[18]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[17]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_2/Mmult_result_P[16]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[35]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[34]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[33]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[32]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[31]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[30]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[29]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[28]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[27]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[26]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[25]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[24]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[23]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[22]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[21]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[20]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[19]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[18]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[17]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_3/Mmult_result_P[16]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[35]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[34]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[33]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[32]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[31]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[30]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[29]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[28]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[27]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[26]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[25]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[24]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[23]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[22]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[21]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[20]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[19]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[18]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[17]_UNCONNECTED ;
  wire \NLW_XLXI_1/mult_1/Mmult_result_P[16]_UNCONNECTED ;
  wire \NLW_XLXI_2/VCC_O_UNCONNECTED ;
  wire \NLW_XLXI_3/BU4_IB_UNCONNECTED ;
  wire \NLW_XLXI_3/VCC_O_UNCONNECTED ;
  wire \NLW_XLXI_4/BU4_IB_UNCONNECTED ;
  wire \NLW_XLXI_4/VCC_O_UNCONNECTED ;
  wire \NLW_XLXI_5/VCC_O_UNCONNECTED ;
  wire [7 : 0] \XLXI_20/data_out ;
  wire [7 : 0] \XLXI_19/data_out ;
  wire [7 : 0] \XLXI_18/data_out ;
  wire [7 : 0] \XLXI_15/data_out ;
  wire [7 : 0] \XLXI_1/r_out ;
  wire [7 : 0] \XLXI_1/i_out ;
  wire [7 : 0] \XLXI_17/data_out ;
  wire [8 : 1] XLXN_69;
  wire [7 : 0] XLXN_47;
  wire [7 : 0] \XLXI_16/data_out ;
  wire [7 : 0] XLXN_53;
  wire [8 : 1] XLXN_71;
  wire [15 : 8] \XLXI_1/r ;
  wire [15 : 8] \XLXI_1/i ;
  wire [8 : 0] \XLXI_1/xmy ;
  wire [15 : 0] \XLXI_1/xmyc ;
  wire [15 : 0] \XLXI_1/cmsy ;
  wire [15 : 0] \XLXI_1/cpsx ;
  wire [0 : 0] \XLXI_2/S ;
  wire [0 : 0] \XLXI_5/S ;
  defparam \XLXI_20/data_out_0 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_0  (
    .I(XLXN_53[0]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [0]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_1 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_1  (
    .I(XLXN_53[1]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [1]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_2 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_2  (
    .I(XLXN_53[2]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [2]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_3 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_3  (
    .I(XLXN_53[3]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [3]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_4 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_4  (
    .I(XLXN_53[4]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [4]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_5 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_5  (
    .I(XLXN_53[5]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [5]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_6 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_6  (
    .I(XLXN_53[6]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [6]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_20/data_out_7 .INIT = 1'b0;
  X_FF \XLXI_20/data_out_7  (
    .I(XLXN_53[7]),
    .CLK(clk_BUFGP),
    .O(\XLXI_20/data_out [7]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_0 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_0  (
    .I(XLXN_71[1]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [0]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_1 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_1  (
    .I(XLXN_71[2]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [1]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_2 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_2  (
    .I(XLXN_71[3]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [2]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_3 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_3  (
    .I(XLXN_71[4]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [3]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_4 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_4  (
    .I(XLXN_71[5]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [4]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_5 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_5  (
    .I(XLXN_71[6]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [5]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_6 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_6  (
    .I(XLXN_71[7]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [6]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_19/data_out_7 .INIT = 1'b0;
  X_FF \XLXI_19/data_out_7  (
    .I(XLXN_71[8]),
    .CLK(clk_BUFGP),
    .O(\XLXI_19/data_out [7]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_18/data_out_0 .INIT = 1'b0;
  X_FF \XLXI_18/data_out_0  (
    .I(XLXN_47[0]),
    .CLK(clk_BUFGP),
    .O(\XLXI_18/data_out [0]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_18/data_out_1 .INIT = 1'b0;
  X_FF \XLXI_18/data_out_1  (
    .I(XLXN_47[1]),
    .CLK(clk_BUFGP),
    .O(\XLXI_18/data_out [1]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_18/data_out_2 .INIT = 1'b0;
  X_FF \XLXI_18/data_out_2  (
    .I(XLXN_47[2]),
    .CLK(clk_BUFGP),
    .O(\XLXI_18/data_out [2]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_18/data_out_3 .INIT = 1'b0;
  X_FF \XLXI_18/data_out_3  (
    .I(XLXN_47[3]),
    .CLK(clk_BUFGP),
    .O(\XLXI_18/data_out [3]),
    .CE(VCC),
    .SET(GND),
    .RST(GND)
  );
  defparam \XLXI_18/data_out_4 .INIT = 1'b0;
  X_FF \XLXI_18/data_out_4  (
    .I(XLXN_47[4]),
    .CLK(clk_BUFGP),