coregen.xml

来自「在ise下设计的蝶形变换程序」· XML 代码 · 共 97 行

<?xml version="1.0" encoding="UTF-8"?>
<RootFolder label="COREGEN" treetype="folder" language="COREGEN">
	<Folder label="VERILOG Component Instantiation" treetype="folder">
		<Template label="jiajia" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
jiajia YourInstanceName (
    .A(A),
    .B(B),
    .S(S));

 
		</Template>
		<Template label="jianjian" treetype="template">
 
 
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
 
jianjian YourInstanceName (
    .A(A),
    .B(B),
    .B_IN(B_IN),
    .S(S));

 
		</Template>
		<Template label="jiajia1" treetype="template">
		</Template>
	</Folder>
	<Folder label="VHDL Component Instantiation" treetype="folder">
		<Template label="jiajia" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component jiajia
    port (
    A: IN std_logic_VECTOR(9 downto 0);
    B: IN std_logic_VECTOR(9 downto 0);
    S: OUT std_logic_VECTOR(10 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : jiajia
        port map (
            A =&gt; A,
            B =&gt; B,
            S =&gt; S);
 
		</Template>
		<Template label="jianjian" treetype="template">
 
 
-- The following code must appear in the VHDL architecture header:
 
component jianjian
    port (
    A: IN std_logic_VECTOR(9 downto 0);
    B: IN std_logic_VECTOR(9 downto 0);
    B_IN: IN std_logic;
    S: OUT std_logic_VECTOR(9 downto 0));
end component;



 
-------------------------------------------------------------
 
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
 
your_instance_name : jianjian
        port map (
            A =&gt; A,
            B =&gt; B,
            B_IN =&gt; B_IN,
            S =&gt; S);
 
		</Template>
		<Template label="jiajia1" treetype="template">
		</Template>
	</Folder>
</RootFolder>