test.vf

在ise下设计的蝶形变换程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1i
//  \   \         Application : sch2verilog
//  /   /         Filename : test.vf
// /___/   /\     Timestamp : 11/21/2006 22:46:47
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: D:\xilinx\bin\nt\sch2verilog.exe -intstyle ise -family spartan3 -w D:/xilinx/lianxi/diexingbianhuan/test.sch test.vf
//Design Name: test
//Device: spartan3
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module test();

   
   
endmodule