lian_map.mrp

在ise下设计的蝶形变换程序

Release 8.1i Map I.24
Xilinx Mapping Report File for Design 'lian'

Design Information
------------------
Command Line   : D:\xilinx\bin\nt\map.exe -ise
D:/xilinx/lianxi/diexingbianhuan/diexingbianhuan.ise -intstyle ise -p
xc3s400-pq208-4 -cm area -pr b -k 4 -c 100 -o lian_map.ncd lian.ngd lian.pcf 
Target Device  : xc3s400
Target Package : pq208
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.34 $
Mapped Date    : Wed Nov 22 09:51:48 2006

Design Summary
--------------
Number of errors   :   2
Number of warnings :   3

Section 1 - Errors
------------------
ERROR:LIT:108 - CI pin of MUXCY symbol "XLXI_3/BU4" (output signal=XLXI_3/N5) is
   not connected but S pin is not constant 0. Please connect the CI pin.
ERROR:LIT:124 - CI pin of XORCY symbol "XLXI_3/BU5" (output signal=XLXN_47<0>)
   is not connected, or driver has been trimmed.

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network XLXI_2/S<0> has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
   more times for the following (max. 5 shown):
   XLXI_5/S<0>
   To see the details of these warning messages, please use the -detail switch.
WARNING:LIT:107 - CI pin of MUXCY symbol "XLXI_3/BU4" (output signal=XLXI_3/N5)
   is not driven, this may produce sub-optimal carry chain.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   6 block(s) removed
   6 block(s) optimized away
   4 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "XLXI_2/S<0>" is sourceless and has been removed.
The signal "XLXI_3/B_IN" is sourceless and has been removed.
The signal "XLXI_4/B_IN" is sourceless and has been removed.
The signal "XLXI_5/S<0>" is sourceless and has been removed.
Unused block "XLXI_2/BU5" (XOR) removed.
Unused block "XLXI_2/VCC" (ONE) removed.
Unused block "XLXI_3/VCC" (ONE) removed.
Unused block "XLXI_4/VCC" (ONE) removed.
Unused block "XLXI_5/BU5" (XOR) removed.
Unused block "XLXI_5/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XLXI_2/GND
GND 		XLXI_3/GND
GND 		XLXI_4/GND
GND 		XLXI_5/GND
GND 		XST_GND
VCC 		XST_VCC