jianjian.xco

在ise下设计的蝶形变换程序

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\xilinx\lianxi\diexingbianhuan
SET speedgrade = -4
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc3s400
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = pq208
SET createndf = False
SET designentry = VHDL
SET devicefamily = spartan3
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Adder_Subtracter family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET create_rpm=true
CSET output_width=10
CSET async_init_value=0
CSET synchronous_settings=none
CSET clock_enable=false
CSET asynchronous_settings=none
CSET bypass=false
CSET ce_overrides=sync_controls_override_ce
CSET ce_override_for_bypass=true
CSET set_clear_priority=clear_overrides_set
CSET overflow_output=false
CSET port_b_width=10
CSET port_b_constant_value=0
CSET component_name=jianjian
CSET port_a_width=10
CSET carry_borrow_output=false
CSET latency=0
CSET operation=subtract
CSET carry_borrow_input=true
CSET port_a_sign=unsigned
CSET bypass_sense=active_high
CSET output_options=non_registered
CSET port_b_constant=false
CSET sync_init_value=0
CSET port_b_sign=unsigned
# END Parameters
GENERATE