test.tfw

在ise下设计的蝶形变换程序

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 8.1i
//  \   \         Application : ISE
//  /   /         Filename : test.tfw
// /___/   /\     Timestamp : Thu Mar 15 21:46:00 2007
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: test
//Device: Xilinx
//
`timescale 1ns/1ps

module test;
    reg [7:0] Aim_in = 8'b00000000;
    reg [7:0] Are_in = 8'b00000000;
    reg [7:0] Bim_in = 8'b00000000;
    reg [7:0] Bre_in = 8'b00000000;
    reg clk = 1'b0;
    reg [8:0] cms_in = 9'b000000000;
    reg [8:0] cps_in = 9'b000000000;
    reg [7:0] c_in = 8'b00001000;
    wire [7:0] Dim_out;
    wire [7:0] Dre_out;
    wire [7:0] Eim_out;
    wire [7:0] Ere_out;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;

    initial    // Clock process for clk
    begin
        #OFFSET;
        forever
        begin
            clk = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clk = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    lian UUT (
        .Aim_in(Aim_in),
        .Are_in(Are_in),
        .Bim_in(Bim_in),
        .Bre_in(Bre_in),
        .clk(clk),
        .cms_in(cms_in),
        .cps_in(cps_in),
        .c_in(c_in),
        .Dim_out(Dim_out),
        .Dre_out(Dre_out),
        .Eim_out(Eim_out),
        .Ere_out(Ere_out));

        integer TX_ERROR = 0;
        
        initial begin  // Open the results file...
            #1200 // Final time:  1200 ns
            if (TX_ERROR == 0) begin
                $display("No errors or warnings.");
                end else begin
                    $display("%d errors found in simulation.", TX_ERROR);
                    end
                    $stop;
                end

                initial begin
                    // -------------  Current Time:  85ns
                    #85;
                    Aim_in = 8'b00010010;
                    Are_in = 8'b00010100;
                    Bim_in = 8'b00000100;
                    cms_in = 9'b000010000;
                    cps_in = 9'b000010000;
                    c_in = 8'b00001100;
                    // -------------------------------------
                    // -------------  Current Time:  285ns
                    #200;
                    Are_in = 8'b00110100;
                    Bim_in = 8'b00000101;
                    Bre_in = 8'b00000110;
                    // -------------------------------------
                    // -------------  Current Time:  315ns
                    #30;
                    CHECK_Dim_out(8'b01111101);
                    CHECK_Dre_out(8'b00010110);
                    CHECK_Eim_out(8'b00101010);
                    CHECK_Ere_out(8'b11111100);
                    // -------------------------------------
                    // -------------  Current Time:  485ns
                    #170;
                    Aim_in = 8'b00010011;
                    Are_in = 8'b00111100;
                    Bre_in = 8'b00000111;
                    cms_in = 9'b000010100;
                    cps_in = 9'b000010100;
                    // -------------------------------------
                    // -------------  Current Time:  515ns
                    #30;
                    CHECK_Dim_out(8'b00001001);
                    CHECK_Dre_out(8'b00011010);
                    CHECK_Eim_out(8'b00010010);
                    CHECK_Ere_out(8'b00110100);
                    // -------------------------------------
                    // -------------  Current Time:  685ns
                    #170;
                    c_in = 8'b00001000;
                    // -------------------------------------
                    // -------------  Current Time:  715ns
                    #30;
                    CHECK_Dre_out(8'b00011110);
                    CHECK_Eim_out(8'b00010011);
                    CHECK_Ere_out(8'b00111100);
                    // -------------------------------------
                end

                task CHECK_Dim_out;
                    input [7:0] NEXT_Dim_out;

                    #0 begin
                        if (NEXT_Dim_out !== Dim_out) begin
                            $display("Error at time=%dns Dim_out=%b, expected=%b", $time, Dim_out, NEXT_Dim_out);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_Dre_out;
                    input [7:0] NEXT_Dre_out;

                    #0 begin
                        if (NEXT_Dre_out !== Dre_out) begin
                            $display("Error at time=%dns Dre_out=%b, expected=%b", $time, Dre_out, NEXT_Dre_out);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_Eim_out;
                    input [7:0] NEXT_Eim_out;

                    #0 begin
                        if (NEXT_Eim_out !== Eim_out) begin
                            $display("Error at time=%dns Eim_out=%b, expected=%b", $time, Eim_out, NEXT_Eim_out);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_Ere_out;
                    input [7:0] NEXT_Ere_out;

                    #0 begin
                        if (NEXT_Ere_out !== Ere_out) begin
                            $display("Error at time=%dns Ere_out=%b, expected=%b", $time, Ere_out, NEXT_Ere_out);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask

            endmodule