ccmul.stx

在ise下设计的蝶形变换程序

Release 8.1i - xst I.24
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 2.42 s | Elapsed : 0.00 / 2.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "ccmul.v" in library work
Compiling verilog include file "sub1.v"
Compiling verilog include file "mult.v"
Module <sub1> compiled
Compiling verilog include file "add.v"
Module <mult> compiled
Compiling verilog include file "sub2.v"
Module <add> compiled
Module <sub2> compiled
Module <ccmul> compiled
No errors in compilation
Analysis of file <"ccmul.prj"> succeeded.
 
CPU : 0.23 / 2.66 s | Elapsed : 1.00 / 3.00 s
 
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Total memory usage is 80492 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)