📄 map.xmsgs
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">XLXI_2/S<0></arg> has no load.
</msg>
<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">1</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">XLXI_5/S<0></arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>
<msg type="info" file="MapLib" num="535" delta="unknown" >The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
<arg fmt="%s" index="1">BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP)</arg>
</msg>
<msg type="warning" file="LIT" num="107" delta="unknown" >CI pin of <arg fmt="%s" index="1">MUXCY symbol "XLXI_3/BU4" (output signal=XLXI_3/N5)</arg> is not driven, this may produce sub-optimal carry chain.
</msg>
<msg type="error" file="LIT" num="108" delta="unknown" >CI pin of <arg fmt="%s" index="1">MUXCY symbol "XLXI_3/BU4" (output signal=XLXI_3/N5)</arg> is not connected but S pin is not constant 0. Please connect the CI pin.
</msg>
<msg type="error" file="LIT" num="124" delta="unknown" >CI pin of <arg fmt="%s" index="1">XORCY symbol "XLXI_3/BU5" (output signal=XLXN_47<0>)</arg> is not connected, or driver has been trimmed.
</msg>
<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
</msg>
</messages>
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