📄 tom08.tan.qmsg
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{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "state.s1 LLCadd\[0\] clk 3.09 ns " "Info: Found hold time violation between source pin or register \"state.s1\" and destination pin or register \"LLCadd\[0\]\" for clock \"clk\" (Hold time is 3.09 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.544 ns + Largest " "Info: + Largest clock skew is 5.544 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.754 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns state.s1 2 REG LC_X9_Y13_N5 7 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.965 ns" { clk state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(0.292 ns) 4.522 ns muxclk~22 3 COMB LC_X8_Y13_N2 14 " "Info: 3: + IC(0.796 ns) + CELL(0.292 ns) = 4.522 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.088 ns" { state.s1 muxclk~22 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.711 ns) 8.754 ns LLCadd\[0\] 4 REG LC_X9_Y12_N6 4 " "Info: 4: + IC(3.521 ns) + CELL(0.711 ns) = 8.754 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd\[0\]'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.232 ns" { muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns 38.92 % " "Info: Total cell delay = 3.407 ns ( 38.92 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.347 ns 61.08 % " "Info: Total interconnect delay = 5.347 ns ( 61.08 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 LLCadd[0] } { 0.0ns 0.0ns 1.03ns 0.796ns 3.521ns } { 0.0ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.210 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns state.s1 2 REG LC_X9_Y13_N5 7 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.741 ns" { clk state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 67.91 % " "Info: Total cell delay = 2.180 ns ( 67.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns 32.09 % " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s1 } { 0.0ns 0.0ns 1.03ns } { 0.0ns 1.469ns 0.711ns } } } } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 LLCadd[0] } { 0.0ns 0.0ns 1.03ns 0.796ns 3.521ns } { 0.0ns 1.469ns 0.935ns 0.292ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s1 } { 0.0ns 0.0ns 1.03ns } { 0.0ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.245 ns - Shortest register register " "Info: - Shortest register to register delay is 2.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s1 1 REG LC_X9_Y13_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.378 ns) + CELL(0.867 ns) 2.245 ns LLCadd\[0\] 2 REG LC_X9_Y12_N6 4 " "Info: 2: + IC(1.378 ns) + CELL(0.867 ns) = 2.245 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd\[0\]'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.245 ns" { state.s1 LLCadd[0] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.867 ns 38.62 % " "Info: Total cell delay = 0.867 ns ( 38.62 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.378 ns 61.38 % " "Info: Total interconnect delay = 1.378 ns ( 61.38 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.245 ns" { state.s1 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.245 ns" { state.s1 LLCadd[0] } { 0.0ns 1.378ns } { 0.0ns 0.867ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } } } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 LLCadd[0] } { 0.0ns 0.0ns 1.03ns 0.796ns 3.521ns } { 0.0ns 1.469ns 0.935ns 0.292ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s1 } { 0.0ns 0.0ns 1.03ns } { 0.0ns 1.469ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.245 ns" { state.s1 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.245 ns" { state.s1 LLCadd[0] } { 0.0ns 1.378ns } { 0.0ns 0.867ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "state.s1 startbutton clk 4.680 ns register " "Info: tsu for register \"state.s1\" (data pin = \"startbutton\", clock pin = \"clk\") is 4.680 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.853 ns + Longest pin register " "Info: + Longest pin to register delay is 7.853 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns startbutton 1 PIN PIN_23 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 4; PIN Node = 'startbutton'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { startbutton } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 12 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.777 ns) + CELL(0.607 ns) 7.853 ns state.s1 2 REG LC_X9_Y13_N5 7 " "Info: 2: + IC(5.777 ns) + CELL(0.607 ns) = 7.853 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "6.384 ns" { startbutton state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.076 ns 26.44 % " "Info: Total cell delay = 2.076 ns ( 26.44 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.777 ns 73.56 % " "Info: Total interconnect delay = 5.777 ns ( 73.56 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "7.853 ns" { startbutton state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.853 ns" { startbutton startbutton~out0 state.s1 } { 0.000ns 0.000ns 5.777ns } { 0.000ns 1.469ns 0.607ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.210 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns state.s1 2 REG LC_X9_Y13_N5 7 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.741 ns" { clk state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 67.91 % " "Info: Total cell delay = 2.180 ns ( 67.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns 32.09 % " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s1 } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "7.853 ns" { startbutton state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.853 ns" { startbutton startbutton~out0 state.s1 } { 0.000ns 0.000ns 5.777ns } { 0.000ns 1.469ns 0.607ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s1 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s1 } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk address\[1\] address\[1\]~reg0 13.388 ns register " "Info: tco from clock \"clk\" to destination pin \"address\[1\]\" through register \"address\[1\]~reg0\" is 13.388 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.754 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns state.s1 2 REG LC_X9_Y13_N5 7 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.965 ns" { clk state.s1 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(0.292 ns) 4.522 ns muxclk~22 3 COMB LC_X8_Y13_N2 14 " "Info: 3: + IC(0.796 ns) + CELL(0.292 ns) = 4.522 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.088 ns" { state.s1 muxclk~22 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.711 ns) 8.754 ns address\[1\]~reg0 4 REG LC_X10_Y12_N2 1 " "Info: 4: + IC(3.521 ns) + CELL(0.711 ns) = 8.754 ns; Loc. = LC_X10_Y12_N2; Fanout = 1; REG Node = 'address\[1\]~reg0'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.232 ns" { muxclk~22 address[1]~reg0 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 68 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns 38.92 % " "Info: Total cell delay = 3.407 ns ( 38.92 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.347 ns 61.08 % " "Info: Total interconnect delay = 5.347 ns ( 61.08 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 address[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 address[1]~reg0 } { 0.000ns 0.000ns 1.030ns 0.796ns 3.521ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 68 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.410 ns + Longest register pin " "Info: + Longest register to pin delay is 4.410 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns address\[1\]~reg0 1 REG LC_X10_Y12_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y12_N2; Fanout = 1; REG Node = 'address\[1\]~reg0'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { address[1]~reg0 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 68 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.302 ns) + CELL(2.108 ns) 4.410 ns address\[1\] 2 PIN PIN_77 0 " "Info: 2: + IC(2.302 ns) + CELL(2.108 ns) = 4.410 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'address\[1\]'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.410 ns" { address[1]~reg0 address[1] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns 47.80 % " "Info: Total cell delay = 2.108 ns ( 47.80 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.302 ns 52.20 % " "Info: Total interconnect delay = 2.302 ns ( 52.20 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.410 ns" { address[1]~reg0 address[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.410 ns" { address[1]~reg0 address[1] } { 0.000ns 2.302ns } { 0.000ns 2.108ns } } } } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 address[1]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 address[1]~reg0 } { 0.000ns 0.000ns 1.030ns 0.796ns 3.521ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.410 ns" { address[1]~reg0 address[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.410 ns" { address[1]~reg0 address[1] } { 0.000ns 2.302ns } { 0.000ns 2.108ns } } } } 0}
{ "Info" "ITDB_TH_RESULT" "state.s0 displaybutton clk -4.341 ns register " "Info: th for register \"state.s0\" (data pin = \"displaybutton\", clock pin = \"clk\") is -4.341 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.210 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.210 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.711 ns) 3.210 ns state.s0 2 REG LC_X9_Y13_N2 5 " "Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N2; Fanout = 5; REG Node = 'state.s0'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.741 ns" { clk state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 67.91 % " "Info: Total cell delay = 2.180 ns ( 67.91 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.030 ns 32.09 % " "Info: Total interconnect delay = 1.030 ns ( 32.09 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s0 } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.566 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.566 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns displaybutton 1 PIN PIN_39 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 4; PIN Node = 'displaybutton'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { displaybutton } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(5.788 ns) + CELL(0.309 ns) 7.566 ns state.s0 2 REG LC_X9_Y13_N2 5 " "Info: 2: + IC(5.788 ns) + CELL(0.309 ns) = 7.566 ns; Loc. = LC_X9_Y13_N2; Fanout = 5; REG Node = 'state.s0'" { } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "6.097 ns" { displaybutton state.s0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.778 ns 23.50 % " "Info: Total cell delay = 1.778 ns ( 23.50 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.788 ns 76.50 % " "Info: Total interconnect delay = 5.788 ns ( 76.50 % )" { } { } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "7.566 ns" { displaybutton state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.566 ns" { displaybutton displaybutton~out0 state.s0 } { 0.000ns 0.000ns 5.788ns } { 0.000ns 1.469ns 0.309ns } } } } 0} } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "3.210 ns" { clk state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.210 ns" { clk clk~out0 state.s0 } { 0.000ns 0.000ns 1.030ns } { 0.000ns 1.469ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "7.566 ns" { displaybutton state.s0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.566 ns" { displaybutton displaybutton~out0 state.s0 } { 0.000ns 0.000ns 5.788ns } { 0.000ns 1.469ns 0.309ns } } } } 0}
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