tom08.tan.qmsg

SRAM 视频采集测试程序 读写时序控制 为解决时钟切换而做的测试程序

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "state.s2 " "Info: Detected ripple clock \"state.s2\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "state.s2" } } } }  } 0} { "Info" "ITAN_GATED_CLK" "muxclk~22 " "Info: Detected gated clock \"muxclk~22\" as buffer" {  } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "muxclk~22" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "state.s1 " "Info: Detected ripple clock \"state.s1\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "state.s1" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "LLC register register LLCadd\[0\] LLCadd\[2\] 275.03 MHz Internal " "Info: Clock \"LLC\" Internal fmax is restricted to 275.03 MHz between source register \"LLCadd\[0\]\" and destination register \"LLCadd\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.818 ns 1.818 ns 3.636 ns " "Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.732 ns + Longest register register " "Info: + Longest register to register delay is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LLCadd\[0\] 1 REG LC_X9_Y12_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd\[0\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { LLCadd[0] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.590 ns) 1.142 ns LLCadd\[2\]~46 2 COMB LC_X9_Y12_N2 1 " "Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X9_Y12_N2; Fanout = 1; COMB Node = 'LLCadd\[2\]~46'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.142 ns" { LLCadd[0] LLCadd[2]~46 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.867 ns) 2.732 ns LLCadd\[2\] 3 REG LC_X8_Y12_N2 2 " "Info: 3: + IC(0.723 ns) + CELL(0.867 ns) = 2.732 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd\[2\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.590 ns" { LLCadd[2]~46 LLCadd[2] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 53.33 % " "Info: Total cell delay = 1.457 ns ( 53.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.275 ns 46.67 % " "Info: Total interconnect delay = 1.275 ns ( 46.67 % )" {  } {  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } { 0.000ns 0.552ns 0.723ns } { 0.000ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LLC destination 8.234 ns + Shortest register " "Info: + Shortest clock path from clock \"LLC\" to destination register is 8.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LLC 1 CLK PIN_38 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 1; CLK Node = 'LLC'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { LLC } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.590 ns) 4.002 ns muxclk~22 2 COMB LC_X8_Y13_N2 14 " "Info: 2: + IC(1.943 ns) + CELL(0.590 ns) = 4.002 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.533 ns" { LLC muxclk~22 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.711 ns) 8.234 ns LLCadd\[2\] 3 REG LC_X8_Y12_N2 2 " "Info: 3: + IC(3.521 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd\[2\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.232 ns" { muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns 33.64 % " "Info: Total cell delay = 2.770 ns ( 33.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.464 ns 66.36 % " "Info: Total interconnect delay = 5.464 ns ( 66.36 % )" {  } {  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.234 ns" { LLC muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.234 ns" { LLC LLC~out0 muxclk~22 LLCadd[2] } { 0.000ns 0.000ns 1.943ns 3.521ns } { 0.000ns 1.469ns 0.590ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "LLC source 8.234 ns - Longest register " "Info: - Longest clock path from clock \"LLC\" to source register is 8.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns LLC 1 CLK PIN_38 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 1; CLK Node = 'LLC'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { LLC } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.943 ns) + CELL(0.590 ns) 4.002 ns muxclk~22 2 COMB LC_X8_Y13_N2 14 " "Info: 2: + IC(1.943 ns) + CELL(0.590 ns) = 4.002 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.533 ns" { LLC muxclk~22 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.711 ns) 8.234 ns LLCadd\[0\] 3 REG LC_X9_Y12_N6 4 " "Info: 3: + IC(3.521 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd\[0\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.232 ns" { muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.770 ns 33.64 % " "Info: Total cell delay = 2.770 ns ( 33.64 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.464 ns 66.36 % " "Info: Total interconnect delay = 5.464 ns ( 66.36 % )" {  } {  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.234 ns" { LLC muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.234 ns" { LLC LLC~out0 muxclk~22 LLCadd[0] } { 0.000ns 0.000ns 1.943ns 3.521ns } { 0.000ns 1.469ns 0.590ns 0.711ns } } }  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.234 ns" { LLC muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.234 ns" { LLC LLC~out0 muxclk~22 LLCadd[2] } { 0.000ns 0.000ns 1.943ns 3.521ns } { 0.000ns 1.469ns 0.590ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.234 ns" { LLC muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.234 ns" { LLC LLC~out0 muxclk~22 LLCadd[0] } { 0.000ns 0.000ns 1.943ns 3.521ns } { 0.000ns 1.469ns 0.590ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } { 0.000ns 0.552ns 0.723ns } { 0.000ns 0.590ns 0.867ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.234 ns" { LLC muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.234 ns" { LLC LLC~out0 muxclk~22 LLCadd[2] } { 0.000ns 0.000ns 1.943ns 3.521ns } { 0.000ns 1.469ns 0.590ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.234 ns" { LLC muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.234 ns" { LLC LLC~out0 muxclk~22 LLCadd[0] } { 0.000ns 0.000ns 1.943ns 3.521ns } { 0.000ns 1.469ns 0.590ns 0.711ns } } }  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { LLCadd[2] } {  } {  } } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register LLCadd\[0\] register LLCadd\[2\] 196.5 MHz 5.089 ns Internal " "Info: Clock \"clk\" has Internal fmax of 196.5 MHz between source register \"LLCadd\[0\]\" and destination register \"LLCadd\[2\]\" (period= 5.089 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.732 ns + Longest register register " "Info: + Longest register to register delay is 2.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LLCadd\[0\] 1 REG LC_X9_Y12_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd\[0\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { LLCadd[0] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.590 ns) 1.142 ns LLCadd\[2\]~46 2 COMB LC_X9_Y12_N2 1 " "Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X9_Y12_N2; Fanout = 1; COMB Node = 'LLCadd\[2\]~46'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.142 ns" { LLCadd[0] LLCadd[2]~46 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.867 ns) 2.732 ns LLCadd\[2\] 3 REG LC_X8_Y12_N2 2 " "Info: 3: + IC(0.723 ns) + CELL(0.867 ns) = 2.732 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd\[2\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.590 ns" { LLCadd[2]~46 LLCadd[2] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.457 ns 53.33 % " "Info: Total cell delay = 1.457 ns ( 53.33 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.275 ns 46.67 % " "Info: Total interconnect delay = 1.275 ns ( 46.67 % )" {  } {  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } { 0.000ns 0.552ns 0.723ns } { 0.000ns 0.590ns 0.867ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-2.096 ns - Smallest " "Info: - Smallest clock skew is -2.096 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.658 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 6.658 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.515 ns) + CELL(0.442 ns) 2.426 ns muxclk~22 2 COMB LC_X8_Y13_N2 14 " "Info: 2: + IC(0.515 ns) + CELL(0.442 ns) = 2.426 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "0.957 ns" { clk muxclk~22 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.711 ns) 6.658 ns LLCadd\[2\] 3 REG LC_X8_Y12_N2 2 " "Info: 3: + IC(3.521 ns) + CELL(0.711 ns) = 6.658 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd\[2\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.232 ns" { muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.622 ns 39.38 % " "Info: Total cell delay = 2.622 ns ( 39.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.036 ns 60.62 % " "Info: Total interconnect delay = 4.036 ns ( 60.62 % )" {  } {  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "6.658 ns" { clk muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.658 ns" { clk clk~out0 muxclk~22 LLCadd[2] } { 0.000ns 0.000ns 0.515ns 3.521ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.754 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 8.754 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "" { clk } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.935 ns) 3.434 ns state.s1 2 REG LC_X9_Y13_N5 7 " "Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.965 ns" { clk state.s1 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(0.292 ns) 4.522 ns muxclk~22 3 COMB LC_X8_Y13_N2 14 " "Info: 3: + IC(0.796 ns) + CELL(0.292 ns) = 4.522 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "1.088 ns" { state.s1 muxclk~22 } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 23 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.521 ns) + CELL(0.711 ns) 8.754 ns LLCadd\[0\] 4 REG LC_X9_Y12_N6 4 " "Info: 4: + IC(3.521 ns) + CELL(0.711 ns) = 8.754 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd\[0\]'" {  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "4.232 ns" { muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.407 ns 38.92 % " "Info: Total cell delay = 3.407 ns ( 38.92 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.347 ns 61.08 % " "Info: Total interconnect delay = 5.347 ns ( 61.08 % )" {  } {  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 LLCadd[0] } { 0.000ns 0.000ns 1.030ns 0.796ns 3.521ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "6.658 ns" { clk muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.658 ns" { clk clk~out0 muxclk~22 LLCadd[2] } { 0.000ns 0.000ns 0.515ns 3.521ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 LLCadd[0] } { 0.000ns 0.000ns 1.030ns 0.796ns 3.521ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "tom08.vhd" "" { Text "F:/tom08/tom08.vhd" 22 -1 0 } }  } 0}  } { { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.732 ns" { LLCadd[0] LLCadd[2]~46 LLCadd[2] } { 0.000ns 0.552ns 0.723ns } { 0.000ns 0.590ns 0.867ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "6.658 ns" { clk muxclk~22 LLCadd[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "6.658 ns" { clk clk~out0 muxclk~22 LLCadd[2] } { 0.000ns 0.000ns 0.515ns 3.521ns } { 0.000ns 1.469ns 0.442ns 0.711ns } } } { "F:/tom08/db/tom08_cmp.qrpt" "" { Report "F:/tom08/db/tom08_cmp.qrpt" Compiler "tom08" "UNKNOWN" "V1" "F:/tom08/db/tom08.quartus_db" { Floorplan "F:/tom08/" "" "8.754 ns" { clk state.s1 muxclk~22 LLCadd[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.754 ns" { clk clk~out0 state.s1 muxclk~22 LLCadd[0] } { 0.000ns 0.000ns 1.030ns 0.796ns 3.521ns } { 0.000ns 1.469ns 0.935ns 0.292ns 0.711ns } } }  } 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 17 " "Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0}