📄 tom08.fit.rpt
字号:
; LLCadd[1] ; 3 ;
; clkadd[1] ; 3 ;
; LLCadd[2] ; 2 ;
; clkadd[2] ; 2 ;
; LLC ; 1 ;
; LLCadd[2]~46 ; 1 ;
; LLCadd[1]~45 ; 1 ;
; clkadd[2]~46 ; 1 ;
; clkadd[1]~45 ; 1 ;
; address~0 ; 1 ;
; address~1 ; 1 ;
; address~2 ; 1 ;
; address[2]~reg0 ; 1 ;
; address[1]~reg0 ; 1 ;
; address[0]~reg0 ; 1 ;
; WE~reg0 ; 1 ;
; OE~reg0 ; 1 ;
+-----------------+---------------+
+----------------------------------------------------+
; Interconnect Usage Summary ;
+----------------------------+-----------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+-----------------------+
; C4s ; 19 / 30,600 ( < 1 % ) ;
; Direct links ; 7 / 43,552 ( < 1 % ) ;
; Global clocks ; 6 / 8 ( 75 % ) ;
; LAB clocks ; 9 / 312 ( 2 % ) ;
; LUT chains ; 0 / 10,854 ( 0 % ) ;
; Local interconnects ; 31 / 43,552 ( < 1 % ) ;
; M4K buffers ; 0 / 1,872 ( 0 % ) ;
; R4s ; 29 / 28,560 ( < 1 % ) ;
+----------------------------+-----------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 2.30) ; Number of LABs (Total = 10) ;
+--------------------------------------------+------------------------------+
; 1 ; 4 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 3 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 10) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 2 ;
; 1 Async. load ; 5 ;
; 1 Clock ; 9 ;
; 1 Clock enable ; 4 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 2.30) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
; 2 ; 2 ;
; 3 ; 1 ;
; 4 ; 3 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 1.60) ; Number of LABs (Total = 10) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 7 ;
; 2 ; 0 ;
; 3 ; 3 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 3.10) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 3 ;
; 3 ; 3 ;
; 4 ; 4 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
Info: Processing started: Sun Apr 29 17:18:01 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off tom08 -c tom08
Info: Selected device EP1C12Q240C8 for design "tom08"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6Q240C8 is compatible
Info: No exact pin location assignment(s) for 9 pins of 9 total pins
Info: Pin OE not assigned to an exact location on the device
Info: Pin WE not assigned to an exact location on the device
Info: Pin address[0] not assigned to an exact location on the device
Info: Pin address[1] not assigned to an exact location on the device
Info: Pin address[2] not assigned to an exact location on the device
Info: Pin LLC not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin startbutton not assigned to an exact location on the device
Info: Pin displaybutton not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources.
Info: Automatically promoted some destinations of signal "clk" to use Global clock in PIN 29
Info: Destination "muxclk~22" may be non-global or may not use global clock
Info: Automatically promoted signal "muxclk~22" to use Global clock
Info: Automatically promoted signal "process0~22" to use Global clock
Info: Automatically promoted some destinations of signal "state.s2" to use Global clock
Info: Destination "state.s2" may be non-global or may not use global clock
Info: Destination "muxclk~22" may be non-global or may not use global clock
Info: Destination "clkadd[0]"
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -