tom08.vhd

SRAM 视频采集测试程序 读写时序控制 为解决时钟切换而做的测试程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
entity tom08 is 
port
(
 LLC:in std_logic;
 clk:in std_logic;
 OE:out std_logic;
 WE:out std_logic;
 startbutton: in std_logic;
 address: out std_logic_vector(2 downto 0);
 displaybutton: in std_logic
 );
 end entity;

 architecture behav of tom08 is 
 type states is (s0,s1,s2);
 signal state :states;
 signal clkadd: std_logic_vector(2 downto 0);
 signal LLCadd: std_logic_vector(2 downto 0);
 signal muxclk:std_logic;
 begin
 process(startbutton,displaybutton,clk)
  begin
if startbutton='1' and displaybutton='1'  then
  
     state<=s0;
       elsif (clk'event and clk='1')then
     case state is 
     when  s0 =>
     if  startbutton='0' and displaybutton='1' then
     state<=s1;
     elsif startbutton='1' and displaybutton='0' then
     state<=s2;
     else state <= s0;
     end if ;
     
     when  s1 =>
     if startbutton='1' and displaybutton='1' then
     state<=s0;
     else
     state<=s1;
     end if;
    when s2 =>
     if startbutton='1' and displaybutton='1' then 
     state<=s0;
     else 
     state<=s2;
     end if;
    end case;
  end if;
end process;

process(state,muxclk)
  begin
    if  state<=s1 then
 
     if (muxclk'event and muxclk='1') then
        OE<='1';
       WE<='0';
     
       address<=LLCadd;
      end if;
     elsif state<=s2 then
      
      if (muxclk'event and muxclk='1') then
        OE<='1';
       WE<='1';
     address<=clkadd;
      end if;

    end if;
  if state<=s0 then
       OE<='0';
       WE<='1';
  end if;
  end process;

 process(muxclk,LLCadd,state)
 begin
  if (muxclk'event and muxclk='1' and state=s1)then
 
       if LLCadd="111" then
          LLCadd<="000";
        else LLCadd<=LLCadd+1;
       end if ;
   end if;
end process;
 
process(muxclk,clkadd,state)
 begin
if (muxclk'event and muxclk='1'  and   state=s2)then
 
     
       if clkadd="111" then
          clkadd<="000";
        else clkadd<=clkadd+1;
       end if ;
   
   end if;
end process;
process(state,LLC,clk)
begin
  if state=s1 then
  muxclk<=LLC;
  elsif state=s2 then
  muxclk<=clk;
 else muxclk<='0';
 end if;
 end process;  
  
 end behav;