tom08.tan.rpt

SRAM 视频采集测试程序 读写时序控制 为解决时钟切换而做的测试程序

Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "state.s2" as buffer
    Info: Detected gated clock "muxclk~22" as buffer
    Info: Detected ripple clock "state.s1" as buffer
Info: Clock "LLC" Internal fmax is restricted to 275.03 MHz between source register "LLCadd[0]" and destination register "LLCadd[2]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.732 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd[0]'
            Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X9_Y12_N2; Fanout = 1; COMB Node = 'LLCadd[2]~46'
            Info: 3: + IC(0.723 ns) + CELL(0.867 ns) = 2.732 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd[2]'
            Info: Total cell delay = 1.457 ns ( 53.33 % )
            Info: Total interconnect delay = 1.275 ns ( 46.67 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "LLC" to destination register is 8.234 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 1; CLK Node = 'LLC'
                Info: 2: + IC(1.943 ns) + CELL(0.590 ns) = 4.002 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'
                Info: 3: + IC(3.521 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd[2]'
                Info: Total cell delay = 2.770 ns ( 33.64 % )
                Info: Total interconnect delay = 5.464 ns ( 66.36 % )
            Info: - Longest clock path from clock "LLC" to source register is 8.234 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_38; Fanout = 1; CLK Node = 'LLC'
                Info: 2: + IC(1.943 ns) + CELL(0.590 ns) = 4.002 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'
                Info: 3: + IC(3.521 ns) + CELL(0.711 ns) = 8.234 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd[0]'
                Info: Total cell delay = 2.770 ns ( 33.64 % )
                Info: Total interconnect delay = 5.464 ns ( 66.36 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock "clk" has Internal fmax of 196.5 MHz between source register "LLCadd[0]" and destination register "LLCadd[2]" (period= 5.089 ns)
    Info: + Longest register to register delay is 2.732 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd[0]'
        Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X9_Y12_N2; Fanout = 1; COMB Node = 'LLCadd[2]~46'
        Info: 3: + IC(0.723 ns) + CELL(0.867 ns) = 2.732 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd[2]'
        Info: Total cell delay = 1.457 ns ( 53.33 % )
        Info: Total interconnect delay = 1.275 ns ( 46.67 % )
    Info: - Smallest clock skew is -2.096 ns
        Info: + Shortest clock path from clock "clk" to destination register is 6.658 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.515 ns) + CELL(0.442 ns) = 2.426 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'
            Info: 3: + IC(3.521 ns) + CELL(0.711 ns) = 6.658 ns; Loc. = LC_X8_Y12_N2; Fanout = 2; REG Node = 'LLCadd[2]'
            Info: Total cell delay = 2.622 ns ( 39.38 % )
            Info: Total interconnect delay = 4.036 ns ( 60.62 % )
        Info: - Longest clock path from clock "clk" to source register is 8.754 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
            Info: 3: + IC(0.796 ns) + CELL(0.292 ns) = 4.522 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'
            Info: 4: + IC(3.521 ns) + CELL(0.711 ns) = 8.754 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd[0]'
            Info: Total cell delay = 3.407 ns ( 38.92 % )
            Info: Total interconnect delay = 5.347 ns ( 61.08 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Micro setup delay of destination is 0.037 ns
Warning: Circuit may not operate. Detected 17 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "state.s1" and destination pin or register "LLCadd[0]" for clock "clk" (Hold time is 3.09 ns)
    Info: + Largest clock skew is 5.544 ns
        Info: + Longest clock path from clock "clk" to destination register is 8.754 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
            Info: 3: + IC(0.796 ns) + CELL(0.292 ns) = 4.522 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'
            Info: 4: + IC(3.521 ns) + CELL(0.711 ns) = 8.754 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd[0]'
            Info: Total cell delay = 3.407 ns ( 38.92 % )
            Info: Total interconnect delay = 5.347 ns ( 61.08 % )
        Info: - Shortest clock path from clock "clk" to source register is 3.210 ns
            Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
            Info: Total cell delay = 2.180 ns ( 67.91 % )
            Info: Total interconnect delay = 1.030 ns ( 32.09 % )
    Info: - Micro clock to output delay of source is 0.224 ns
    Info: - Shortest register to register delay is 2.245 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
        Info: 2: + IC(1.378 ns) + CELL(0.867 ns) = 2.245 ns; Loc. = LC_X9_Y12_N6; Fanout = 4; REG Node = 'LLCadd[0]'
        Info: Total cell delay = 0.867 ns ( 38.62 % )
        Info: Total interconnect delay = 1.378 ns ( 61.38 % )
    Info: + Micro hold delay of destination is 0.015 ns
Info: tsu for register "state.s1" (data pin = "startbutton", clock pin = "clk") is 4.680 ns
    Info: + Longest pin to register delay is 7.853 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_23; Fanout = 4; PIN Node = 'startbutton'
        Info: 2: + IC(5.777 ns) + CELL(0.607 ns) = 7.853 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
        Info: Total cell delay = 2.076 ns ( 26.44 % )
        Info: Total interconnect delay = 5.777 ns ( 73.56 % )
    Info: + Micro setup delay of destination is 0.037 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.210 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
        Info: Total cell delay = 2.180 ns ( 67.91 % )
        Info: Total interconnect delay = 1.030 ns ( 32.09 % )
Info: tco from clock "clk" to destination pin "address[1]" through register "address[1]~reg0" is 13.388 ns
    Info: + Longest clock path from clock "clk" to source register is 8.754 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.030 ns) + CELL(0.935 ns) = 3.434 ns; Loc. = LC_X9_Y13_N5; Fanout = 7; REG Node = 'state.s1'
        Info: 3: + IC(0.796 ns) + CELL(0.292 ns) = 4.522 ns; Loc. = LC_X8_Y13_N2; Fanout = 14; COMB Node = 'muxclk~22'
        Info: 4: + IC(3.521 ns) + CELL(0.711 ns) = 8.754 ns; Loc. = LC_X10_Y12_N2; Fanout = 1; REG Node = 'address[1]~reg0'
        Info: Total cell delay = 3.407 ns ( 38.92 % )
        Info: Total interconnect delay = 5.347 ns ( 61.08 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 4.410 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y12_N2; Fanout = 1; REG Node = 'address[1]~reg0'
        Info: 2: + IC(2.302 ns) + CELL(2.108 ns) = 4.410 ns; Loc. = PIN_77; Fanout = 0; PIN Node = 'address[1]'
        Info: Total cell delay = 2.108 ns ( 47.80 % )
        Info: Total interconnect delay = 2.302 ns ( 52.20 % )
Info: th for register "state.s0" (data pin = "displaybutton", clock pin = "clk") is -4.341 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.210 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.030 ns) + CELL(0.711 ns) = 3.210 ns; Loc. = LC_X9_Y13_N2; Fanout = 5; REG Node = 'state.s0'
        Info: Total cell delay = 2.180 ns ( 67.91 % )
        Info: Total interconnect delay = 1.030 ns ( 32.09 % )
    Info: + Micro hold delay of destination is 0.015 ns
    Info: - Shortest pin to register delay is 7.566 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_39; Fanout = 4; PIN Node = 'displaybutton'
        Info: 2: + IC(5.788 ns) + CELL(0.309 ns) = 7.566 ns; Loc. = LC_X9_Y13_N2; Fanout = 5; REG Node = 'state.s0'
        Info: Total cell delay = 1.778 ns ( 23.50 % )
        Info: Total interconnect delay = 5.788 ns ( 76.50 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 3 warnings
    Info: Processing ended: Sun Apr 29 17:18:23 2007
    Info: Elapsed time: 00:00:02