📄 tom08.tan.rpt
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Timing Analyzer report for tom08
Sun Apr 29 17:18:23 2007
Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'LLC'
6. Clock Setup: 'clk'
7. Clock Hold: 'clk'
8. tsu
9. tco
10. th
11. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------+------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------+------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.680 ns ; startbutton ; state.s1 ; ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 13.388 ns ; address[1]~reg0 ; address[1] ; clk ; ; 0 ;
; Worst-case th ; N/A ; None ; -4.341 ns ; displaybutton ; state.s0 ; ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 196.50 MHz ( period = 5.089 ns ) ; LLCadd[0] ; LLCadd[2] ; clk ; clk ; 0 ;
; Clock Setup: 'LLC' ; N/A ; None ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[0] ; LLCadd[2] ; LLC ; LLC ; 0 ;
; Clock Hold: 'clk' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; state.s1 ; LLCadd[0] ; clk ; clk ; 17 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 17 ;
+------------------------------+------------------------------------------+---------------+------------------------------------------------+-----------------+------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C12Q240C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; LLC ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
; clk ; ; User Pin ; NONE ; 0.000 ns ; 0.000 ns ; NONE ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'LLC' ;
+-------+------------------------------------------------+-----------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[0] ; LLCadd[2] ; LLC ; LLC ; None ; None ; 2.732 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[1] ; clkadd[2] ; LLC ; LLC ; None ; None ; 2.727 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[0] ; clkadd[2] ; LLC ; LLC ; None ; None ; 2.569 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[1] ; LLCadd[2] ; LLC ; LLC ; None ; None ; 2.545 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[1] ; address[1]~reg0 ; LLC ; LLC ; None ; None ; 2.006 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[0] ; clkadd[1] ; LLC ; LLC ; None ; None ; 1.982 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[0] ; LLCadd[1] ; LLC ; LLC ; None ; None ; 1.979 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[0] ; address[0]~reg0 ; LLC ; LLC ; None ; None ; 1.438 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[0] ; address~2 ; LLC ; LLC ; None ; None ; 1.391 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[2] ; address~0 ; LLC ; LLC ; None ; None ; 1.382 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[1] ; address~1 ; LLC ; LLC ; None ; None ; 1.045 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[1] ; LLCadd[1] ; LLC ; LLC ; None ; None ; 1.029 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[2] ; LLCadd[2] ; LLC ; LLC ; None ; None ; 1.014 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; LLCadd[0] ; LLCadd[0] ; LLC ; LLC ; None ; None ; 0.851 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[0] ; clkadd[0] ; LLC ; LLC ; None ; None ; 0.848 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[2] ; address[2]~reg0 ; LLC ; LLC ; None ; None ; 0.841 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[2] ; clkadd[2] ; LLC ; LLC ; None ; None ; 0.837 ns ;
; N/A ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; clkadd[1] ; clkadd[1] ; LLC ; LLC ; None ; None ; 0.836 ns ;
+-------+------------------------------------------------+-----------+-----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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