📄 std_1c20.ptf
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}
TARGET sim
{
ext_ram
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
contents_info = "";
}
SLAVE s1
{
PORT_WIRING
{
PORT data
{
width = "32";
is_shared = "1";
direction = "inout";
type = "data";
BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
{
component_pin = "U35.7,U35.8,U35.9,U35.10,U35.13,U35.14,U35.15,U35.16,U35.29,U35.30,U35.31,U35.32,U35.35,U35.36,U35.37,U35.38,U36.7,U36.8,U36.9,U36.10,U36.13,U36.14,U36.15,U36.16,U36.29,U36.30,U36.31,U36.32,U36.35,U36.36,U36.37,U36.38";
pin_assignment = "C6,E6,B6,A6,F7,E7,B7,A7,D7,C7,F8,E8,B8,A8,D8,C8,B9,A9,D9,C9,E9,E10,B10,A10,F10,C10,D10,C11,D11,B11,A11,E11";
}
}
PORT address
{
width = "18";
is_shared = "1";
direction = "input";
type = "address";
lsb = "2";
BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
{
component_pin = "U35.1,U35.2,U35.3,U35.4,U35.5,U35.18,U35.19,U35.20,U35.21,U35.22,U35.23,U35.24,U35.25,U35.26,U35.27,U35.42,U35.43,U35.44";
pin_assignment = "D5,D6,C5,B5,C2,D2,D4,D1,E4,E5,F3,E3,E2,F4,F5,F2,F1,F6";
}
}
PORT read_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "read_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
{
component_pin = "U35.41";
pin_assignment = "Y17";
}
}
PORT write_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "write_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
{
component_pin = "U35.17";
pin_assignment = "U16";
}
}
PORT be_n
{
width = "4";
is_shared = "0";
direction = "input";
type = "byteenable_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
{
component_pin = "U35.39,U35.40,U36.39,U36.40";
pin_assignment = "V17,V16,W16,T16";
}
}
PORT select_n
{
width = "1";
is_shared = "0";
direction = "input";
type = "chipselect_n";
BOARD_COMPONENT altera_nios_dev_board_cyclone_1c20
{
component_pin = "U35.6";
pin_assignment = "W17";
}
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon_tristate";
Is_Memory_Device = "1";
Address_Alignment = "dynamic";
Data_Width = "32";
Address_Width = "18";
Has_IRQ = "0";
Read_Wait_States = "0ns";
Write_Wait_States = "0ns";
Hold_Time = "half";
Base_Address = "0x02000000";
Address_Span = "1048576";
MASTERED_BY ext_ram_bus/tristate_master
{
priority = "1";
}
Setup_Time = "0";
IRQ_MASTER cpu/data_master
{
IRQ_Number = "NC";
}
Is_Base_Locked = "1";
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "0";
Make_Memory_Model = "1";
Default_Module_Name = "sram";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Clock_Source = "clk";
Top_Level_Ports_Are_Enumerated = "1";
}
}
MODULE epcs_controller
{
class = "altera_avalon_epcs_flash_controller";
class_version = "2.1";
SLAVE epcs_control_port
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Is_Printable_Device = "0";
Address_Alignment = "dynamic";
Is_Memory_Device = "1";
Address_Width = "9";
Data_Width = "32";
Has_IRQ = "1";
Read_Wait_States = "1";
Write_Wait_States = "1";
MASTERED_BY cpu/instruction_master
{
priority = "1";
}
MASTERED_BY cpu/data_master
{
priority = "1";
}
IRQ_MASTER cpu/data_master
{
IRQ_Number = "5";
}
Base_Address = "0x02100000";
Is_Nonvolatile_Storage = "1";
}
WIZARD_SCRIPT_ARGUMENTS
{
class = "altera_avalon_epcs_flash_controller";
flash_reference_designator = "U59";
}
PORT_WIRING
{
PORT address
{
direction = "input";
type = "address";
width = "9";
Is_Enabled = "1";
}
PORT chipselect
{
direction = "input";
type = "chipselect";
width = "1";
Is_Enabled = "1";
}
PORT clk
{
direction = "input";
type = "clk";
width = "1";
Is_Enabled = "1";
}
PORT dataavailable
{
direction = "output";
type = "dataavailable";
width = "1";
Is_Enabled = "1";
}
PORT endofpacket
{
direction = "output";
type = "endofpacket";
width = "1";
Is_Enabled = "1";
}
PORT irq
{
direction = "output";
type = "irq";
width = "1";
Is_Enabled = "1";
}
PORT read_n
{
direction = "input";
type = "read_n";
width = "1";
Is_Enabled = "1";
}
PORT readdata
{
direction = "output";
type = "readdata";
width = "32";
Is_Enabled = "1";
}
PORT readyfordata
{
direction = "output";
type = "readyfordata";
width = "1";
Is_Enabled = "1";
}
PORT reset_n
{
direction = "input";
type = "reset_n";
width = "1";
Is_Enabled = "1";
}
PORT write_n
{
direction = "input";
type = "write_n";
width = "1";
Is_Enabled = "1";
}
PORT writedata
{
direction = "input";
type = "writedata";
width = "32";
Is_Enabled = "1";
}
PORT data_from_cpu
{
Is_Enabled = "0";
direction = "input";
type = "writedata";
width = "16";
}
PORT data_to_cpu
{
Is_Enabled = "0";
direction = "output";
type = "readdata";
width = "16";
}
PORT epcs_select
{
Is_Enabled = "0";
direction = "input";
type = "chipselect";
width = "1";
}
PORT mem_addr
{
Is_Enabled = "0";
direction = "input";
type = "address";
width = "3";
}
}
}
SYSTEM_BUILDER_INFO
{
Is_Enabled = "1";
Instantiate_In_System_Module = "1";
Required_Device_Family = "CYCLONE,CYCLONEII,STRATIXII";
Fixed_Module_Name = "epcs_controller";
View
{
MESSAGES
{
}
Is_Collapsed = "1";
}
Top_Level_Ports_Are_Enumerated = "1";
Clock_Source = "clk";
}
WIZARD_SCRIPT_ARGUMENTS
{
databits = "8";
targetclock = "20";
clockunits = "MHz";
clockmult = "1000000";
numslaves = "1";
ismaster = "1";
clockpolarity = "0";
clockphase = "0";
lsbfirst = "0";
extradelay = "1";
targetssdelay = "100";
delayunits = "us";
delaymult = "1e-006";
prefix = "epcs_";
MAKE
{
MACRO
{
EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1:0=)";
EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_TMP1 = "$(ALT_SIM_OPTIMIZE:1=RUN_ON_HDL_SIMULATOR_ONLY_)";
EPCS_RELOCATE = "$(EPCS_RELOCATE_TMP:1=--relocate)";
EPCS_RELOCATE_TMP = "$(BOOTS_FROM_EPCS:0=)";
}
MASTER cpu
{
MACRO
{
CPU_CLASS = "altera_nios2";
CPU_RESET_ADDRESS = "0x0";
BOOTS_FROM_EPCS = "0";
BOOT_COPIER_EPCS = "boot_loader_epcs.srec";
}
}
TARGET epcs
{
epcs_controller
{
All_Depends_On = "0";
Command1 = "sof2flash --flash=U59 --offset=0x0 --output=epcs.flash $(SOF) --epcs ";
Command2 = "nios2-flash-programmer --input=epcs.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs $(EPCS_RELOCATE) ";
Dependency = "";
Is_Phony = "1";
Target_File = "epcs_controller_boot_rom_epcs_configuration";
}
}
TARGET flashfiles
{
epcs_controller
{
Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then echo Post-processing to create $(notdir $@) ; elf2flash --input=$(ELF) --flash=U59 --boot=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir $(CPU_CLASS))/$(BOOT_COPIER_EPCS) --outfile=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sim_optimize=$(ALT_SIM_OPTIMIZE) --epcs --base=0x0 --end=0x7FFFFFFF ; fi";
Dependency = "$(ELF)";
Target_File = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
}
}
TARGET programflash
{
epcs_controller
{
All_Depends_On = "0";
Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs ; fi";
Dependency = "$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash";
Is_Phony = "1";
Target_File = "epcs_controller_boot_rom_programflash";
}
}
TARGET delete_placeholder_warning
{
epcs_controller
{
Command1 = "rm -f $(SIMDIR)/contents_file_warning.txt";
Is_Phony = "1";
Target_File = "do_delete_placeholder_warning";
}
}
TARGET programflashnoelfdependency
{
epcs_controller
{
All_Depends_On = "0";
Command1 = "@if [ $(BOOTS_FROM_EPCS) -eq 1 ]; then nios2-flash-programmer --input=$(EPCS_CONTROLLER_BOOT_ROM_FLASHTARGET_ALT_SIM_PREFIX)epcs_controller_boot_rom.flash --sof=$(shell $(QUARTUS_ROOTDIR)/sopc_builder/bin/find_sopc_component_dir altera_nios_dev_board_cyclone_1c20)/system/altera_nios_dev_board_cyclone_1c20.sof --device=1 $(JTAG_CABLE) --epcs ; fi";
Is_Phony = "1";
Target_File = "epcs_controller_boot_rom_programflashnoelf";
}
}
TARGET sim
{
epcs_controller
{
Command1 = "if [ ! -d $(SIMDIR) ]; then mkdir $(SIMDIR) ; fi";
Command2 = "@echo Hardware simulation is not enabled for the target SOPC Builder system. Skipping creation of hardware simulation model contents and simulation symbol files. \\(Note: This does not affect the instruction set simulator.\\)";
Command3 = "touch $(SIMDIR)/dummy_file";
Dependency = "$(ELF)";
Target_File = "$(SIMDIR)/dummy_file";
}
}
}
clockunit = "kHz";
delayunit = "us";
register_offset = "0x200";
}
HDL_INFO
{
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__⌨️ 快捷键说明
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