ctr9851.vhd

AD9851的vhdl串行控制程序（9851系统时钟内部指定）

--功能：控制9851。串行输入控制
--输入9851的输出时钟频率，9851系统时钟内部指定


--对一个signal赋高阻是毫无意义的
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.STD_LOGIC_UNSIGNED.all;



entity ctr9851 is
port(
	
	Reset:in std_logic;				--复位时钟，FPGA上电复位
	Clk:in std_logic;				--同步时钟
	IUpdate:in std_logic;			--时钟频率改变确认脉冲
    IClkRateData:in std_logic_vector(23 DOWNTO 0);			--9851输出的时钟频率
    
	O9851ctrData:		out std_logic_vector(3 DOWNTO 0) 	--9851的串行控制脚

      );
end;


architecture ctr9851_arc of ctr9851 is

signal sOldDDIORDY0: std_logic;
signal sOldDDIORDY1: std_logic;
signal sIData0: std_logic_vector(15 DOWNTO 0);
signal sIData1: std_logic_vector(15 DOWNTO 0);
signal sClkSum: std_logic_vector(2 DOWNTO 0);
signal sClkSubSum: std_logic_vector(7 DOWNTO 0);
--signal sClkSubSum: std_logic_vector(1 DOWNTO 0);
signal s9851FreqCtrWord: std_logic_vector(31 DOWNTO 0);
signal s9851FreqCtrWordCopy: std_logic_vector(39 DOWNTO 0);
signal sClrIUpdate: std_logic;
signal sIUpdate: std_logic;
component Dvide9851 
	PORT
	(
		denom		: IN STD_LOGIC_VECTOR (28 DOWNTO 0);
		numer		: IN STD_LOGIC_VECTOR (55 DOWNTO 0);
		quotient		: OUT STD_LOGIC_VECTOR (55 DOWNTO 0);
		remain		: OUT STD_LOGIC_VECTOR (28 DOWNTO 0)
	);

end component;

begin
u0:Dvide9851 
	PORT map
	(
		denom		=>  "0" & X"ABA9500"  ,
		numer		=> IClkRateData & X"00000000",
		quotient(31 DOWNTO 0)	=> s9851FreqCtrWord(31 DOWNTO 0)
		--remain		=> 
	);
	
process(IUpdate,sClrIUpdate)
begin
  if( sClrIUpdate = '1' ) then
    sIUpdate <= '0';
  elsif( IUpdate'event and IUpdate = '1' ) then  --局部时钟上升沿 and Clk='1'
  	sIUpdate <= '1';
  end if;
end process;



process(Reset,Clk)
begin
  if( Reset = '1' ) then
    sClkSum <= "000";
    O9851ctrData <= X"0";
    sClkSubSum <= X"00";
  elsif( Clk'event and Clk = '1' ) then  --局部时钟上升沿 and Clk='1'
  	sClrIUpdate <= '0';
    case sClkSum is
      when "000" => --复位9851
        O9851ctrData <= X"8";
        if ( sClkSubSum = X"0F" ) then
		  sClkSum <= sClkSum +1;
		  sClkSubSum <= X"00";
		else
		  sClkSubSum <= sClkSubSum +1;
		end if;
	  when "001" => --设置9851串行方式
		case sClkSubSum is
      	  when X"00" =>   
			O9851ctrData <= X"2";
			sClkSubSum <= sClkSubSum +1;
		  when X"01" =>   
			O9851ctrData <= X"0";
			sClkSubSum <= sClkSubSum +1;
		  when X"02" =>   
			O9851ctrData <= X"4";
			sClkSubSum <= sClkSubSum +1;
		  when others =>   
			O9851ctrData <= X"0";
			sClkSubSum <= X"00";
			sClkSum <= sClkSum +1;
		end case;
	  when "010" => --等待9851数据改变
		O9851ctrData <= X"0";
        if ( sIUpdate = '1') then
		  sClkSum <= sClkSum +1;
		  
		end if;
		sClkSubSum <= X"00";
	  when "011" => --等待9851的频率控制字计算完成		
	    O9851ctrData <= X"0"; 
        if ( sClkSubSum = X"FF" ) then
		  sClkSum <= sClkSum +1;
		  sClkSubSum <= X"00";
		  s9851FreqCtrWordCopy(31 DOWNTO 0) <= s9851FreqCtrWord(31 DOWNTO 0);
		  s9851FreqCtrWordCopy(39 DOWNTO 32) <= X"01";
		else
		  sClkSubSum <= sClkSubSum +1;
		end if;
	  when "100" => --进行9851的频率设置		
	    O9851ctrData(0) <= s9851FreqCtrWordCopy(0); 
	    --O9851ctrData(1) <= s9851FreqCtrWordCopy(0); 
		O9851ctrData(2) <= '0'; 
		O9851ctrData(3) <= '0'; 
		if( sClkSubSum(7 downto 2) = "101000" ) then 
		  sClkSum <= sClkSum +1;
		  sClkSubSum <= X"00";
		else
		  sClkSubSum <= sClkSubSum +1;
		  case sClkSubSum(1 downto 0) is
			when "00"=>
			  O9851ctrData(1) <= '0';
			when "01"=>
			  O9851ctrData(1) <= '1';
			when "10"=>
			  O9851ctrData(1) <= '0';
			when "11"=>
			  O9851ctrData(1) <= '0';
			  for i in 0 to 38 loop
	  			s9851FreqCtrWordCopy(i) <= s9851FreqCtrWordCopy(i+1) ;
			  end loop;
		  end case;
		end if;
	  when "101" => --进行9851的频率设置生效			
	    O9851ctrData <= X"4";
	    sClkSum <= sClkSum +1;
	    sClrIUpdate <= '1';
	  when others => --回待命状态	
	 	O9851ctrData <= X"0";
	    sClkSum <= "010";
  end case;
	  

    --sIData0 <= IDiskData;
  end if;
end process;




--with IDDIORDY select 
   --OData <=  	sIData0 when '0',--
          --  sIData1  when others;



end ctr9851_arc;