prescale_counter.gfl

FPGA-CPLD_DesignTool(example7),需要的朋友可以下载

# xst flow : RunXST
prescale_counter.syr
prescale_counter.ngr
prescale_counter.prj
prescale_counter.sprj
prescale_counter.ana
prescale_counter.stx
prescale_counter.cmd_log
prescale_counter.ngc
# Implmentation : Translate
__projnav/ngdbuild.err
__projnav/ednTOngd_tcl.rsp
h:\my_designs\prescale_counter/_ngo
prescale_counter.ngd
prescale_counter_ngdbuild.nav
prescale_counter.bld
.untf
prescale_counter.cmd_log
# Implementation : Map
prescale_counter.nc1
prescale_counter.mrp
prescale_counter.pcf
prescale_counter.ngm
prescale_counter_map.ngm
prescale_counter.mdf
prescale_counter_map.ncd
__projnav/map.log
prescale_counter.cmd_log
# Implmentation : Post-Place & Route Timing
__projnav/ncdTOtwr_tcl.rsp
__projnav/posttrc.log
prescale_counter.twr
prescale_counter.twx
prescale_counter.tsi
prescale_counter.cmd_log
# Implmentation : Generate Post-Place & Route Static Timing
__projnav/nc1TOncd_tcl.rsp
prescale_counter.ncd
prescale_counter.par
prescale_counter.pad
prescale_counter.dly
prescale_counter.xpi
prescale_counter.grf
prescale_counter.itr
prescale_counter_last_par.ncd
__projnav/par.log
prescale_counter.cmd_log
# Generate Programming File
__projnav/prescale_counter_ncdTOut_tcl.rsp
__projnav/bitgen.rsp
bitgen.ut
prescale_counter.ut
# Generate Programming File
prescale_counter.bgn
prescale_counter.rbt
prescale_counter.ll
prescale_counter.msk
prescale_counter.drc
prescale_counter.nky
prescale_counter.bit
prescale_counter.bin
prescale_counter.isc
prescale_counter.cmd_log
# Verilog : PDCL (jhdparse)
__projnav/testbench_jhdparse_tcl.rsp
# Implementation : Ngdanno (post-par)
__projnav/ncdTOnga_par_tcl.rsp
prescale_counter.nga
prescale_counter.alf
prescale_counter.arf
prescale_counter.nga_par
prescale_counter.cmd_log
# Implementation : Generate Post-Par Simulation Model
prescale_counter_timesim.v
prescale_counter_timesim.sdf
prescale_counter_timesim.sdf
prescale_counter_timesim.v
__projnav/prescale_counter.err
__projnav/ngd2ver.log
prescale_counter.versim_par
prescale_counter.cmd_log
# ModelSim : Simulate Post-Place & Route Verilog Model
testbench.tdo
# ModelSim : Simulate Post-Place & Route Verilog Model
vsim.wlf