iq_pn_gen.mrp

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Release 4.2i - Map E.35
Xilinx Mapping Report File for Design 'iq_pn_gen'

Design Information
------------------
Command Line   : map -p xcv300-bg432-6 -cm area -k 4 -c 100 -tx off
iq_pn_gen.ngd 
Target Device  : xv300
Target Package : bg432
Target Speed   : -6
Mapper Version : virtex -- $Revision: 1.58 $
Mapped Date    : Sun Dec 01 19:59:05 2002

Design Summary
--------------
   Number of errors:      0
   Number of warnings:    0
   Number of Slices:                  6 out of  3,072    1%
   Number of Slices containing
      unrelated logic:                0 out of      6    0%
   Number of Slice Flip Flops:        6 out of  6,144    1%
   Total Number 4 input LUTs:         8 out of  6,144    1%
      Number used as LUTs:                          3
      Number used as Shift registers:               5
   Number of bonded IOBs:             6 out of    316    1%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
Total equivalent gate count for design:  706
Additional JTAG gate count for IOBs:  336

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group Summary
Section 10 - Modular Design Summary

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------

Section 3 - Informational
-------------------------
INFO:MapLib:62 - All of the external outputs in this design are using slew rate
   limited output drivers. The delay on speed critical outputs can be
   dramatically reduced by designating them as fast outputs in the schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away

Section 5 - Removed Logic
-------------------------

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn_i                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| DataIn_q                           | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| FillSel                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| ShiftEn                            | IOB     | INPUT     | LVTTL       |          |      |          |          |       |
| pn_out_i                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| pn_out_q                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group Summary
------------------------------
No area groups were found in this design.

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.