__projnav.log

FPGA-CPLD_DesignTool,事例程序3-4陆续上传请需要的朋友下载

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_iq_pn_gen.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    D:/Xilinx/data/simprim.lst
Scanning    D:/Xilinx/verilog/src/iSE/unisim_comp.v
Scanning    iq_pn_gen.v
Writing iq_pn_gen.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

Starting: 'jhdparse @_pn_gen_srl_test.jp'