iq_pn_gen.syr

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Release 4.2i - xst E.35
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : iq_pn_gen.prj

---- Target Parameters
Target Device                      : xcv300-bg432-6
Output File Name                   : iq_pn_gen
Output Format                      : NGC
Target Technology                  : virtex

---- Source Options
Top Module Name                    : iq_pn_gen
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES
ROM Extraction                     : Yes
RAM Extraction                     : Yes
RAM Style                          : Auto
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Add Generic Clock Buffer(BUFG)     : 4
Global Maximum Fanout              : 100
Register Duplication               : YES
Move First FlipFlop Stage          : YES
Move Last FlipFlop Stage           : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Speed Grade                        : 6

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : No
Global Optimization                : AllClockNets
Write Timing Constraints           : No

=========================================================================

 
Compiling source file : iq_pn_gen.prj
Compiling included source file 'iq_pn_gen.v'
Module <iq_pn_gen> compiled.
Continuing compilation of source file 'iq_pn_gen.prj'
Compiling included source file 'D:/Xilinx/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'iq_pn_gen.prj'
No errors in compilation
Analysis of file <iq_pn_gen.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <iq_pn_gen>.
Module <iq_pn_gen> is correct for synthesis.

Synthesizing Unit <iq_pn_gen>.
    Related source file is iq_pn_gen.v.
    Found 1-bit xor2 for signal <par_fdbk_i>.
    Found 1-bit xor4 for signal <par_fdbk_q>.
    Found 12-bit shift register for signal <srl_i<5>>.
    Found 5-bit shift register for signal <srl_i<0>>.
    Found 8-bit shift register for signal <srl_q<9>>.
    Found 1-bit register for signal <srl_q<5>>.
    Found 1-bit register for signal <srl_q<4>>.
    Found 4-bit shift register for signal <srl_q<0>>.
    Found 2 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
	inferred   5 Shift register(s).
	inferred   2 Xor(s).
Unit <iq_pn_gen> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 1
  1-bit register                   : 1
# Shift Registers                  : 5
  8-bit shift register             : 1
  4-bit shift register             : 2
  12-bit shift register            : 1
  5-bit shift register             : 1
# Multiplexers                     : 2
  2-to-1 multiplexer               : 2
# Xors                             : 2
  1-bit xor2                       : 1
  1-bit xor4                       : 1

=========================================================================


Starting low level synthesis...
Optimizing unit <iq_pn_gen> ...

Building and optimizing final netlist ...

WARNING:Xst:637 - Naming conflict during MERGE on SEQUENTIAL: renaming Mshreg_srl_q_9 to Mshreg_srl_q_91.
WARNING:Xst:637 - Naming conflict during MERGE on SEQUENTIAL: renaming Mshreg_srl_q_5 to Mshreg_srl_q_51.
WARNING:Xst:637 - Naming conflict during MERGE on SEQUENTIAL: renaming Mshreg_srl_q_0 to Mshreg_srl_q_01.
WARNING:Xst:637 - Naming conflict during MERGE on SEQUENTIAL: renaming Mshreg_srl_i_5 to Mshreg_srl_i_51.
WARNING:Xst:637 - Naming conflict during MERGE on SEQUENTIAL: renaming Mshreg_srl_i_0 to Mshreg_srl_i_01.
=========================================================================
Final Results
Top Level Output File Name         : iq_pn_gen
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : virtex
Keep Hierarchy                     : No
Macro Generator                    : macro+

Macro Statistics
# Registers                        : 1
  1-bit register                   : 1
# Shift Registers                  : 5
  8-bit shift register             : 1
  4-bit shift register             : 2
  12-bit shift register            : 1
  5-bit shift register             : 1

Design Statistics
# IOs                              : 7

Cell Usage :
# BELS                             : 6
#      GND                         : 1
#      LUT2                        : 1
#      LUT3                        : 1
#      LUT4                        : 1
#      LUT4_L                      : 1
#      VCC                         : 1
# FlipFlops/Latches                : 6
#      FDE                         : 6
# Shifters                         : 5
#      SRL16E                      : 5
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 6
#      IBUF                        : 4
#      OBUF                        : 2
=========================================================================


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 11    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.100ns (Maximum Frequency: 243.902MHz)
   Minimum input arrival time before clock: 4.367ns
   Maximum output required time after clock: 7.058ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               4.100ns (Levels of Logic = 0)
  Source:            Mshreg_srl_q_9_srl_1
  Destination:       Mshreg_srl_q_91
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: Mshreg_srl_q_9_srl_1 to Mshreg_srl_q_91
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    SRL16E:CLK->Q          1   2.150   1.035  Mshreg_srl_q_9_srl_1 (Mshreg_srl_q_9_xstmacro_int_tempname2)
    FDE:D                      0.915          Mshreg_srl_q_91
    ----------------------------------------
    Total                      4.100ns (3.065ns logic, 1.035ns route)
                                       (74.8% logic, 25.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              4.367ns (Levels of Logic = 3)
  Source:            FillSel
  Destination:       Mshreg_srl_q_9_srl_1
  Destination Clock: clk rising

  Data Path: FillSel to Mshreg_srl_q_9_srl_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    IBUF:I->O              3   0.768   1.332  FillSel_IBUF (FillSel_IBUF)
    LUT2:I0->O             1   0.573   1.035  I_1_LUT_6 (N31)
    LUT3:I2->O             1   0.573   0.000  I_Mmux_lfsr_in_q_Result (N33)
    SRL16E:D                   0.086          Mshreg_srl_q_9_srl_1
    ----------------------------------------
    Total                      4.367ns (2.000ns logic, 2.367ns route)
                                       (45.8% logic, 54.2% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              7.058ns (Levels of Logic = 1)
  Source:            Mshreg_srl_i_01
  Destination:       pn_out_i
  Source Clock:      clk rising

  Data Path: Mshreg_srl_i_01 to pn_out_i
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    FDE:C->Q               2   1.065   1.206  Mshreg_srl_i_01 (Mshreg_srl_i_01)
    OBUF:I->O                  4.787          pn_out_i_OBUF (pn_out_i)
    ----------------------------------------
    Total                      7.058ns (5.852ns logic, 1.206ns route)
                                       (82.9% logic, 17.1% route)

=========================================================================
CPU : 5.31 / 5.69 s | Elapsed : 5.00 / 5.00 s
 
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